Lines Matching refs:adev
41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, in amdgpu_gfx_mec_queue_to_bit() argument
46 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
47 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
48 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, in amdgpu_queue_mask_bit_to_mec_queue() argument
57 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
58 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
59 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
60 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
61 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, in amdgpu_gfx_is_mec_queue_enabled() argument
68 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue), in amdgpu_gfx_is_mec_queue_enabled()
69 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, in amdgpu_gfx_me_queue_to_bit() argument
77 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
78 * adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
79 bit += pipe * adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_me_queue_to_bit()
85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, in amdgpu_gfx_bit_to_me_queue() argument
88 *queue = bit % adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_bit_to_me_queue()
89 *pipe = (bit / adev->gfx.me.num_queue_per_pipe) in amdgpu_gfx_bit_to_me_queue()
90 % adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_bit_to_me_queue()
91 *me = (bit / adev->gfx.me.num_queue_per_pipe) in amdgpu_gfx_bit_to_me_queue()
92 / adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_bit_to_me_queue()
95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, in amdgpu_gfx_is_me_queue_enabled() argument
98 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue), in amdgpu_gfx_is_me_queue_enabled()
99 adev->gfx.me.queue_bitmap); in amdgpu_gfx_is_me_queue_enabled()
146 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev) in amdgpu_gfx_is_graphics_multipipe_capable() argument
148 return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1; in amdgpu_gfx_is_graphics_multipipe_capable()
151 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) in amdgpu_gfx_is_compute_multipipe_capable() argument
161 if (adev->asic_type == CHIP_POLARIS11) in amdgpu_gfx_is_compute_multipipe_capable()
164 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_compute_multipipe_capable()
167 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, in amdgpu_gfx_is_high_priority_graphics_queue() argument
176 if (amdgpu_gfx_is_graphics_multipipe_capable(adev) && in amdgpu_gfx_is_high_priority_graphics_queue()
177 adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) { in amdgpu_gfx_is_high_priority_graphics_queue()
181 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue); in amdgpu_gfx_is_high_priority_graphics_queue()
182 if (ring == &adev->gfx.gfx_ring[bit]) in amdgpu_gfx_is_high_priority_graphics_queue()
189 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, in amdgpu_gfx_is_high_priority_compute_queue() argument
195 if (adev->gfx.num_compute_rings > 1 && in amdgpu_gfx_is_high_priority_compute_queue()
196 ring == &adev->gfx.compute_ring[0]) in amdgpu_gfx_is_high_priority_compute_queue()
202 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) in amdgpu_gfx_compute_queue_acquire() argument
205 bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev); in amdgpu_gfx_compute_queue_acquire()
206 int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec * in amdgpu_gfx_compute_queue_acquire()
207 adev->gfx.mec.num_queue_per_pipe, in amdgpu_gfx_compute_queue_acquire()
208 adev->gfx.num_compute_rings); in amdgpu_gfx_compute_queue_acquire()
213 pipe = i % adev->gfx.mec.num_pipe_per_mec; in amdgpu_gfx_compute_queue_acquire()
214 queue = (i / adev->gfx.mec.num_pipe_per_mec) % in amdgpu_gfx_compute_queue_acquire()
215 adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_compute_queue_acquire()
217 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue, in amdgpu_gfx_compute_queue_acquire()
218 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_compute_queue_acquire()
223 set_bit(i, adev->gfx.mec.queue_bitmap); in amdgpu_gfx_compute_queue_acquire()
226 …dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGP… in amdgpu_gfx_compute_queue_acquire()
229 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) in amdgpu_gfx_graphics_queue_acquire() argument
232 bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev); in amdgpu_gfx_graphics_queue_acquire()
233 int max_queues_per_me = adev->gfx.me.num_pipe_per_me * in amdgpu_gfx_graphics_queue_acquire()
234 adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_graphics_queue_acquire()
240 pipe = i % adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_graphics_queue_acquire()
241 queue = (i / adev->gfx.me.num_pipe_per_me) % in amdgpu_gfx_graphics_queue_acquire()
242 adev->gfx.me.num_queue_per_pipe; in amdgpu_gfx_graphics_queue_acquire()
244 set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue, in amdgpu_gfx_graphics_queue_acquire()
245 adev->gfx.me.queue_bitmap); in amdgpu_gfx_graphics_queue_acquire()
249 set_bit(i, adev->gfx.me.queue_bitmap); in amdgpu_gfx_graphics_queue_acquire()
253 adev->gfx.num_gfx_rings = in amdgpu_gfx_graphics_queue_acquire()
254 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in amdgpu_gfx_graphics_queue_acquire()
257 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, in amdgpu_gfx_kiq_acquire() argument
263 queue_bit = adev->gfx.mec.num_mec in amdgpu_gfx_kiq_acquire()
264 * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_kiq_acquire()
265 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_kiq_acquire()
268 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) in amdgpu_gfx_kiq_acquire()
271 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); in amdgpu_gfx_kiq_acquire()
288 dev_err(adev->dev, "Failed to find a queue for KIQ\n"); in amdgpu_gfx_kiq_acquire()
292 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, in amdgpu_gfx_kiq_init_ring() argument
296 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init_ring()
301 ring->adev = NULL; in amdgpu_gfx_kiq_init_ring()
304 ring->doorbell_index = adev->doorbell_index.kiq; in amdgpu_gfx_kiq_init_ring()
306 r = amdgpu_gfx_kiq_acquire(adev, ring); in amdgpu_gfx_kiq_init_ring()
313 r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, in amdgpu_gfx_kiq_init_ring()
316 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); in amdgpu_gfx_kiq_init_ring()
326 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) in amdgpu_gfx_kiq_fini() argument
328 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_fini()
333 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, in amdgpu_gfx_kiq_init() argument
338 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init()
340 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, in amdgpu_gfx_kiq_init()
344 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); in amdgpu_gfx_kiq_init()
352 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); in amdgpu_gfx_kiq_init()
360 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, in amdgpu_gfx_mqd_sw_init() argument
367 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_mqd_sw_init()
368 if (!adev->enable_mes_kiq && !ring->mqd_obj) { in amdgpu_gfx_mqd_sw_init()
374 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, in amdgpu_gfx_mqd_sw_init()
378 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); in amdgpu_gfx_mqd_sw_init()
383 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL); in amdgpu_gfx_mqd_sw_init()
384 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) in amdgpu_gfx_mqd_sw_init()
385 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
388 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { in amdgpu_gfx_mqd_sw_init()
390 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in amdgpu_gfx_mqd_sw_init()
391 ring = &adev->gfx.gfx_ring[i]; in amdgpu_gfx_mqd_sw_init()
393 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, in amdgpu_gfx_mqd_sw_init()
397 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in amdgpu_gfx_mqd_sw_init()
402 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); in amdgpu_gfx_mqd_sw_init()
403 if (!adev->gfx.me.mqd_backup[i]) in amdgpu_gfx_mqd_sw_init()
404 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
410 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_init()
411 ring = &adev->gfx.compute_ring[i]; in amdgpu_gfx_mqd_sw_init()
413 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, in amdgpu_gfx_mqd_sw_init()
417 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); in amdgpu_gfx_mqd_sw_init()
422 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); in amdgpu_gfx_mqd_sw_init()
423 if (!adev->gfx.mec.mqd_backup[i]) in amdgpu_gfx_mqd_sw_init()
424 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_mqd_sw_init()
431 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev) in amdgpu_gfx_mqd_sw_fini() argument
436 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { in amdgpu_gfx_mqd_sw_fini()
437 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in amdgpu_gfx_mqd_sw_fini()
438 ring = &adev->gfx.gfx_ring[i]; in amdgpu_gfx_mqd_sw_fini()
439 kfree(adev->gfx.me.mqd_backup[i]); in amdgpu_gfx_mqd_sw_fini()
446 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_fini()
447 ring = &adev->gfx.compute_ring[i]; in amdgpu_gfx_mqd_sw_fini()
448 kfree(adev->gfx.mec.mqd_backup[i]); in amdgpu_gfx_mqd_sw_fini()
454 ring = &adev->gfx.kiq.ring; in amdgpu_gfx_mqd_sw_fini()
455 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); in amdgpu_gfx_mqd_sw_fini()
461 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) in amdgpu_gfx_disable_kcq() argument
463 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_disable_kcq()
470 spin_lock(&adev->gfx.kiq.ring_lock); in amdgpu_gfx_disable_kcq()
472 adev->gfx.num_compute_rings)) { in amdgpu_gfx_disable_kcq()
473 spin_unlock(&adev->gfx.kiq.ring_lock); in amdgpu_gfx_disable_kcq()
477 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_gfx_disable_kcq()
478 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], in amdgpu_gfx_disable_kcq()
481 if (adev->gfx.kiq.ring.sched.ready && !adev->job_hang) in amdgpu_gfx_disable_kcq()
483 spin_unlock(&adev->gfx.kiq.ring_lock); in amdgpu_gfx_disable_kcq()
488 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, in amdgpu_queue_mask_bit_to_set_resource_bit() argument
494 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); in amdgpu_queue_mask_bit_to_set_resource_bit()
501 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) in amdgpu_gfx_enable_kcq() argument
503 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_enable_kcq()
504 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in amdgpu_gfx_enable_kcq()
512 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in amdgpu_gfx_enable_kcq()
523 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); in amdgpu_gfx_enable_kcq()
528 spin_lock(&adev->gfx.kiq.ring_lock); in amdgpu_gfx_enable_kcq()
530 adev->gfx.num_compute_rings + in amdgpu_gfx_enable_kcq()
534 spin_unlock(&adev->gfx.kiq.ring_lock); in amdgpu_gfx_enable_kcq()
538 if (adev->enable_mes) in amdgpu_gfx_enable_kcq()
542 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_gfx_enable_kcq()
543 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); in amdgpu_gfx_enable_kcq()
546 spin_unlock(&adev->gfx.kiq.ring_lock); in amdgpu_gfx_enable_kcq()
564 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) in amdgpu_gfx_off_ctrl() argument
568 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) in amdgpu_gfx_off_ctrl()
571 mutex_lock(&adev->gfx.gfx_off_mutex); in amdgpu_gfx_off_ctrl()
578 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0)) in amdgpu_gfx_off_ctrl()
581 adev->gfx.gfx_off_req_count--; in amdgpu_gfx_off_ctrl()
583 if (adev->gfx.gfx_off_req_count == 0 && in amdgpu_gfx_off_ctrl()
584 !adev->gfx.gfx_off_state) { in amdgpu_gfx_off_ctrl()
586 if (adev->in_s0ix) in amdgpu_gfx_off_ctrl()
588 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, in amdgpu_gfx_off_ctrl()
592 if (adev->gfx.gfx_off_req_count == 0) { in amdgpu_gfx_off_ctrl()
593 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); in amdgpu_gfx_off_ctrl()
595 if (adev->gfx.gfx_off_state && in amdgpu_gfx_off_ctrl()
596 !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) { in amdgpu_gfx_off_ctrl()
597 adev->gfx.gfx_off_state = false; in amdgpu_gfx_off_ctrl()
599 if (adev->gfx.funcs->init_spm_golden) { in amdgpu_gfx_off_ctrl()
600 dev_dbg(adev->dev, in amdgpu_gfx_off_ctrl()
602 amdgpu_gfx_init_spm_golden(adev); in amdgpu_gfx_off_ctrl()
607 adev->gfx.gfx_off_req_count++; in amdgpu_gfx_off_ctrl()
611 mutex_unlock(&adev->gfx.gfx_off_mutex); in amdgpu_gfx_off_ctrl()
614 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value) in amdgpu_set_gfx_off_residency() argument
618 mutex_lock(&adev->gfx.gfx_off_mutex); in amdgpu_set_gfx_off_residency()
620 r = amdgpu_dpm_set_residency_gfxoff(adev, value); in amdgpu_set_gfx_off_residency()
622 mutex_unlock(&adev->gfx.gfx_off_mutex); in amdgpu_set_gfx_off_residency()
627 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value) in amdgpu_get_gfx_off_residency() argument
631 mutex_lock(&adev->gfx.gfx_off_mutex); in amdgpu_get_gfx_off_residency()
633 r = amdgpu_dpm_get_residency_gfxoff(adev, value); in amdgpu_get_gfx_off_residency()
635 mutex_unlock(&adev->gfx.gfx_off_mutex); in amdgpu_get_gfx_off_residency()
640 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value) in amdgpu_get_gfx_off_entrycount() argument
644 mutex_lock(&adev->gfx.gfx_off_mutex); in amdgpu_get_gfx_off_entrycount()
646 r = amdgpu_dpm_get_entrycount_gfxoff(adev, value); in amdgpu_get_gfx_off_entrycount()
648 mutex_unlock(&adev->gfx.gfx_off_mutex); in amdgpu_get_gfx_off_entrycount()
653 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) in amdgpu_get_gfx_off_status() argument
658 mutex_lock(&adev->gfx.gfx_off_mutex); in amdgpu_get_gfx_off_status()
660 r = amdgpu_dpm_get_status_gfxoff(adev, value); in amdgpu_get_gfx_off_status()
662 mutex_unlock(&adev->gfx.gfx_off_mutex); in amdgpu_get_gfx_off_status()
667 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_gfx_ras_late_init() argument
671 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_gfx_ras_late_init()
672 if (!amdgpu_persistent_edc_harvesting_supported(adev)) in amdgpu_gfx_ras_late_init()
673 amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX); in amdgpu_gfx_ras_late_init()
675 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_gfx_ras_late_init()
679 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in amdgpu_gfx_ras_late_init()
683 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); in amdgpu_gfx_ras_late_init()
688 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_gfx_ras_late_init()
692 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, in amdgpu_gfx_process_ras_data_cb() argument
702 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { in amdgpu_gfx_process_ras_data_cb()
703 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); in amdgpu_gfx_process_ras_data_cb()
704 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && in amdgpu_gfx_process_ras_data_cb()
705 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_gfx_process_ras_data_cb()
706 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_gfx_process_ras_data_cb()
707 amdgpu_ras_reset_gpu(adev); in amdgpu_gfx_process_ras_data_cb()
712 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, in amdgpu_gfx_cp_ecc_error_irq() argument
716 struct ras_common_if *ras_if = adev->gfx.ras_if; in amdgpu_gfx_cp_ecc_error_irq()
727 amdgpu_ras_interrupt_dispatch(adev, &ih_data); in amdgpu_gfx_cp_ecc_error_irq()
731 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) in amdgpu_kiq_rreg() argument
736 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_kiq_rreg()
739 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_kiq_rreg()
742 if (adev->mes.ring.sched.ready) in amdgpu_kiq_rreg()
743 return amdgpu_mes_rreg(adev, reg); in amdgpu_kiq_rreg()
748 if (amdgpu_device_wb_get(adev, ®_val_offs)) { in amdgpu_kiq_rreg()
771 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) in amdgpu_kiq_rreg()
784 value = adev->wb.wb[reg_val_offs]; in amdgpu_kiq_rreg()
785 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
794 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
795 dev_err(adev->dev, "failed to read reg:%x\n", reg); in amdgpu_kiq_rreg()
799 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) in amdgpu_kiq_wreg() argument
804 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_kiq_wreg()
809 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_kiq_wreg()
812 if (adev->mes.ring.sched.ready) { in amdgpu_kiq_wreg()
813 amdgpu_mes_wreg(adev, reg, v); in amdgpu_kiq_wreg()
837 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) in amdgpu_kiq_wreg()
856 dev_err(adev->dev, "failed to write reg:%x\n", reg); in amdgpu_kiq_wreg()
859 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) in amdgpu_gfx_get_num_kcq() argument
864 …dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by use… in amdgpu_gfx_get_num_kcq()
870 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, in amdgpu_gfx_cp_init_microcode() argument
882 adev->gfx.pfp_fw->data; in amdgpu_gfx_cp_init_microcode()
883 adev->gfx.pfp_fw_version = in amdgpu_gfx_cp_init_microcode()
885 adev->gfx.pfp_feature_version = in amdgpu_gfx_cp_init_microcode()
887 ucode_fw = adev->gfx.pfp_fw; in amdgpu_gfx_cp_init_microcode()
892 adev->gfx.pfp_fw->data; in amdgpu_gfx_cp_init_microcode()
893 adev->gfx.pfp_fw_version = in amdgpu_gfx_cp_init_microcode()
895 adev->gfx.pfp_feature_version = in amdgpu_gfx_cp_init_microcode()
897 ucode_fw = adev->gfx.pfp_fw; in amdgpu_gfx_cp_init_microcode()
903 adev->gfx.pfp_fw->data; in amdgpu_gfx_cp_init_microcode()
904 ucode_fw = adev->gfx.pfp_fw; in amdgpu_gfx_cp_init_microcode()
909 adev->gfx.me_fw->data; in amdgpu_gfx_cp_init_microcode()
910 adev->gfx.me_fw_version = in amdgpu_gfx_cp_init_microcode()
912 adev->gfx.me_feature_version = in amdgpu_gfx_cp_init_microcode()
914 ucode_fw = adev->gfx.me_fw; in amdgpu_gfx_cp_init_microcode()
919 adev->gfx.me_fw->data; in amdgpu_gfx_cp_init_microcode()
920 adev->gfx.me_fw_version = in amdgpu_gfx_cp_init_microcode()
922 adev->gfx.me_feature_version = in amdgpu_gfx_cp_init_microcode()
924 ucode_fw = adev->gfx.me_fw; in amdgpu_gfx_cp_init_microcode()
930 adev->gfx.me_fw->data; in amdgpu_gfx_cp_init_microcode()
931 ucode_fw = adev->gfx.me_fw; in amdgpu_gfx_cp_init_microcode()
936 adev->gfx.ce_fw->data; in amdgpu_gfx_cp_init_microcode()
937 adev->gfx.ce_fw_version = in amdgpu_gfx_cp_init_microcode()
939 adev->gfx.ce_feature_version = in amdgpu_gfx_cp_init_microcode()
941 ucode_fw = adev->gfx.ce_fw; in amdgpu_gfx_cp_init_microcode()
946 adev->gfx.mec_fw->data; in amdgpu_gfx_cp_init_microcode()
947 adev->gfx.mec_fw_version = in amdgpu_gfx_cp_init_microcode()
949 adev->gfx.mec_feature_version = in amdgpu_gfx_cp_init_microcode()
951 ucode_fw = adev->gfx.mec_fw; in amdgpu_gfx_cp_init_microcode()
957 adev->gfx.mec_fw->data; in amdgpu_gfx_cp_init_microcode()
958 ucode_fw = adev->gfx.mec_fw; in amdgpu_gfx_cp_init_microcode()
963 adev->gfx.mec2_fw->data; in amdgpu_gfx_cp_init_microcode()
964 adev->gfx.mec2_fw_version = in amdgpu_gfx_cp_init_microcode()
966 adev->gfx.mec2_feature_version = in amdgpu_gfx_cp_init_microcode()
968 ucode_fw = adev->gfx.mec2_fw; in amdgpu_gfx_cp_init_microcode()
974 adev->gfx.mec2_fw->data; in amdgpu_gfx_cp_init_microcode()
975 ucode_fw = adev->gfx.mec2_fw; in amdgpu_gfx_cp_init_microcode()
980 adev->gfx.mec_fw->data; in amdgpu_gfx_cp_init_microcode()
981 adev->gfx.mec_fw_version = in amdgpu_gfx_cp_init_microcode()
983 adev->gfx.mec_feature_version = in amdgpu_gfx_cp_init_microcode()
985 ucode_fw = adev->gfx.mec_fw; in amdgpu_gfx_cp_init_microcode()
993 adev->gfx.mec_fw->data; in amdgpu_gfx_cp_init_microcode()
994 ucode_fw = adev->gfx.mec_fw; in amdgpu_gfx_cp_init_microcode()
1001 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_cp_init_microcode()
1002 info = &adev->firmware.ucode[ucode_id]; in amdgpu_gfx_cp_init_microcode()
1005 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE); in amdgpu_gfx_cp_init_microcode()