57  * - 3.0.0 - initial driver
58  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
59  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
61  * - 3.3.0 - Add VM support for UVD on supported hardware.
62  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
63  * - 3.5.0 - Add support for new UVD_NO_OP register.
64  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
65  * - 3.7.0 - Add support for VCE clock list packet
66  * - 3.8.0 - Add support raster config init in the kernel
67  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
68  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
69  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
70  * - 3.12.0 - Add query for double offchip LDS buffers
71  * - 3.13.0 - Add PRT support
72  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
73  * - 3.15.0 - Export more gpu info for gfx9
74  * - 3.16.0 - Add reserved vmid support
75  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
76  * - 3.18.0 - Export gpu always on cu bitmap
77  * - 3.19.0 - Add support for UVD MJPEG decode
78  * - 3.20.0 - Add support for local BOs
79  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
80  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
81  * - 3.23.0 - Add query for VRAM lost counter
82  * - 3.24.0 - Add high priority compute support for gfx9
83  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
84  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
85  * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
86  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
87  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
88  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
89  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
90  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
91  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
92  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
93  * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
94  * - 3.36.0 - Allow reading more status registers on si/cik
95  * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
96  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
97  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
98  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
99  * - 3.41.0 - Add video codec query
100  * - 3.42.0 - Add 16bpc fixed point display support
101  * - 3.43.0 - Add device hot plug/unplug support
102  * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
103  * - 3.45.0 - Add context ioctl stable pstate interface
104  * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
105  * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106  * - 3.48.0 - Add IP discovery version info to HW INFO
107  *   3.49.0 - Add gang submit into CS IOCTL
111 #define KMS_DRIVER_PATCHLEVEL	0
128 uint amdgpu_ip_block_mask = 0xffffffff;
143 u64 amdgpu_cg_mask = 0xffffffffffffffff;
144 uint amdgpu_pg_mask = 0xffffffff;
153 uint amdgpu_pp_feature_mask = 0xfff7bfff;
163  * FBC (bit 0) disabled by default
191 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
207 			amdgpu_drv_delayed_reset_work_handler, 0),
210 uint amdgpu_ras_mask = 0xffffffff;
214 	.period = 0x0, /* default to 0x0 (timeout disable) */
219  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
226 …* Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visi…
250 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disa…
255 …* Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to di…
257 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
262 …lay Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
264 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
269  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
271 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
276  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
278 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
283 …* To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The defaul…
285 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
293  * multiple values specified. 0 and negative values are invalidated. They will be adjusted
306 		" 0: keep default value. negative: infinity timeout), "
314  * (0 = disable, 1 = enable)
317 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
323  * Set to 0 to force direct loading if supported by the ASIC.  Set
327 …lc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if su…
332  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
334 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
341  * Setting the value to 0 disables this functionality.
343 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0…
351 …* the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on …
358 …wer Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
361 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
366 …* Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disa…
368 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
394 …* Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No st…
396 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always…
401  * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
403 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
408 …* Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only…
409 …* is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, neve…
411 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB))…
416  * Enable experimental hw support (1 = enable). The default is 0 (disabled).
418 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
423 …* Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (a…
425 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
461  * The default is 0 (automatic for each asic).
463 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
469  * The default is 0 (automatic for each asic).
471 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
476 …* Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT …
477  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
479 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
484 …* Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT …
485  * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
487 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
492 …* Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default i…
494 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 =…
517  * Set how much time allow a job hang and not drop it. The default is 0.
519 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
524 …* Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (au…
526 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)…
529 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 …
534 …* Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disable…
536 …covery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto…
541 …nable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
543 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
548  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
550 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (d…
555  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
558 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ra…
572 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout…
578 …* set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using r…
584 int amdgpu_si_support = 0;
585 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
597 …* set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using r…
603 int amdgpu_cik_support = 0;
604 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
615 …* It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is…
616  * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
619 	"reserve gtt for smu debug usage, 0 = disable,"
620 		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
628 …either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enab…
633  * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
636 	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
642  * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
651  * (0 = disabled (default), 1 = enabled)
654 	"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
660  * (0 = disabled (default), 1 = enabled)
663 	"Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
670  * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
673 	"Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
686  * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
689 	"Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
703 …"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for de…
713 …"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for …
718  * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
723 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
743 	"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
750  * Default value is 0, diabled.
755 …"Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable,…
769 	"Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
773  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
778 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
815 … to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The defa…
817 int amdgpu_no_queue_eviction_on_vm_fault = 0;
818 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction,…
847 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
854  * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
859  * Defaults to 0, or disabled. Userspace can still override this level later
863 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
867 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
875  * The default value: 0 (off).  TODO: change to auto till it is completed.
877 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
882  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
884 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = m…
893 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad …
896 …l compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)…
903 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
908  * Used to override pptable id. id = 0 use VBIOS pptable.
909  * id > 0 use the soft pptable with specicfied id.
912 …"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft p…
920 	0x4354,
921 	0x4358,
922 	0x4554,
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924 	0x4744,
925 	0x4749,
926 	0x474C,
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1215 	0x68a1,
1216 	0x68a8,
1217 	0x68a9,
1218 	0x68b0,
1219 	0x68b8,
1220 	0x68b9,
1221 	0x68ba,
1222 	0x68be,
1223 	0x68bf,
1224 	0x68c0,
1225 	0x68c1,
1226 	0x68c7,
1227 	0x68c8,
1228 	0x68c9,
1229 	0x68d8,
1230 	0x68d9,
1231 	0x68da,
1232 	0x68de,
1233 	0x68e0,
1234 	0x68e1,
1235 	0x68e4,
1236 	0x68e5,
1237 	0x68e8,
1238 	0x68e9,
1239 	0x68f1,
1240 	0x68f2,
1241 	0x68f8,
1242 	0x68f9,
1243 	0x68fa,
1244 	0x68fe,
1245 	0x7100,
1246 	0x7101,
1247 	0x7102,
1248 	0x7103,
1249 	0x7104,
1250 	0x7105,
1251 	0x7106,
1252 	0x7108,
1253 	0x7109,
1254 	0x710A,
1255 	0x710B,
1256 	0x710C,
1257 	0x710E,
1258 	0x710F,
1259 	0x7140,
1260 	0x7141,
1261 	0x7142,
1262 	0x7143,
1263 	0x7144,
1264 	0x7145,
1265 	0x7146,
1266 	0x7147,
1267 	0x7149,
1268 	0x714A,
1269 	0x714B,
1270 	0x714C,
1271 	0x714D,
1272 	0x714E,
1273 	0x714F,
1274 	0x7151,
1275 	0x7152,
1276 	0x7153,
1277 	0x715E,
1278 	0x715F,
1279 	0x7180,
1280 	0x7181,
1281 	0x7183,
1282 	0x7186,
1283 	0x7187,
1284 	0x7188,
1285 	0x718A,
1286 	0x718B,
1287 	0x718C,
1288 	0x718D,
1289 	0x718F,
1290 	0x7193,
1291 	0x7196,
1292 	0x719B,
1293 	0x719F,
1294 	0x71C0,
1295 	0x71C1,
1296 	0x71C2,
1297 	0x71C3,
1298 	0x71C4,
1299 	0x71C5,
1300 	0x71C6,
1301 	0x71C7,
1302 	0x71CD,
1303 	0x71CE,
1304 	0x71D2,
1305 	0x71D4,
1306 	0x71D5,
1307 	0x71D6,
1308 	0x71DA,
1309 	0x71DE,
1310 	0x7200,
1311 	0x7210,
1312 	0x7211,
1313 	0x7240,
1314 	0x7243,
1315 	0x7244,
1316 	0x7245,
1317 	0x7246,
1318 	0x7247,
1319 	0x7248,
1320 	0x7249,
1321 	0x724A,
1322 	0x724B,
1323 	0x724C,
1324 	0x724D,
1325 	0x724E,
1326 	0x724F,
1327 	0x7280,
1328 	0x7281,
1329 	0x7283,
1330 	0x7284,
1331 	0x7287,
1332 	0x7288,
1333 	0x7289,
1334 	0x728B,
1335 	0x728C,
1336 	0x7290,
1337 	0x7291,
1338 	0x7293,
1339 	0x7297,
1340 	0x7834,
1341 	0x7835,
1342 	0x791e,
1343 	0x791f,
1344 	0x793f,
1345 	0x7941,
1346 	0x7942,
1347 	0x796c,
1348 	0x796d,
1349 	0x796e,
1350 	0x796f,
1351 	0x9400,
1352 	0x9401,
1353 	0x9402,
1354 	0x9403,
1355 	0x9405,
1356 	0x940A,
1357 	0x940B,
1358 	0x940F,
1359 	0x94A0,
1360 	0x94A1,
1361 	0x94A3,
1362 	0x94B1,
1363 	0x94B3,
1364 	0x94B4,
1365 	0x94B5,
1366 	0x94B9,
1367 	0x9440,
1368 	0x9441,
1369 	0x9442,
1370 	0x9443,
1371 	0x9444,
1372 	0x9446,
1373 	0x944A,
1374 	0x944B,
1375 	0x944C,
1376 	0x944E,
1377 	0x9450,
1378 	0x9452,
1379 	0x9456,
1380 	0x945A,
1381 	0x945B,
1382 	0x945E,
1383 	0x9460,
1384 	0x9462,
1385 	0x946A,
1386 	0x946B,
1387 	0x947A,
1388 	0x947B,
1389 	0x9480,
1390 	0x9487,
1391 	0x9488,
1392 	0x9489,
1393 	0x948A,
1394 	0x948F,
1395 	0x9490,
1396 	0x9491,
1397 	0x9495,
1398 	0x9498,
1399 	0x949C,
1400 	0x949E,
1401 	0x949F,
1402 	0x94C0,
1403 	0x94C1,
1404 	0x94C3,
1405 	0x94C4,
1406 	0x94C5,
1407 	0x94C6,
1408 	0x94C7,
1409 	0x94C8,
1410 	0x94C9,
1411 	0x94CB,
1412 	0x94CC,
1413 	0x94CD,
1414 	0x9500,
1415 	0x9501,
1416 	0x9504,
1417 	0x9505,
1418 	0x9506,
1419 	0x9507,
1420 	0x9508,
1421 	0x9509,
1422 	0x950F,
1423 	0x9511,
1424 	0x9515,
1425 	0x9517,
1426 	0x9519,
1427 	0x9540,
1428 	0x9541,
1429 	0x9542,
1430 	0x954E,
1431 	0x954F,
1432 	0x9552,
1433 	0x9553,
1434 	0x9555,
1435 	0x9557,
1436 	0x955f,
1437 	0x9580,
1438 	0x9581,
1439 	0x9583,
1440 	0x9586,
1441 	0x9587,
1442 	0x9588,
1443 	0x9589,
1444 	0x958A,
1445 	0x958B,
1446 	0x958C,
1447 	0x958D,
1448 	0x958E,
1449 	0x958F,
1450 	0x9590,
1451 	0x9591,
1452 	0x9593,
1453 	0x9595,
1454 	0x9596,
1455 	0x9597,
1456 	0x9598,
1457 	0x9599,
1458 	0x959B,
1459 	0x95C0,
1460 	0x95C2,
1461 	0x95C4,
1462 	0x95C5,
1463 	0x95C6,
1464 	0x95C7,
1465 	0x95C9,
1466 	0x95CC,
1467 	0x95CD,
1468 	0x95CE,
1469 	0x95CF,
1470 	0x9610,
1471 	0x9611,
1472 	0x9612,
1473 	0x9613,
1474 	0x9614,
1475 	0x9615,
1476 	0x9616,
1477 	0x9640,
1478 	0x9641,
1479 	0x9642,
1480 	0x9643,
1481 	0x9644,
1482 	0x9645,
1483 	0x9647,
1484 	0x9648,
1485 	0x9649,
1486 	0x964a,
1487 	0x964b,
1488 	0x964c,
1489 	0x964e,
1490 	0x964f,
1491 	0x9710,
1492 	0x9711,
1493 	0x9712,
1494 	0x9713,
1495 	0x9714,
1496 	0x9715,
1497 	0x9802,
1498 	0x9803,
1499 	0x9804,
1500 	0x9805,
1501 	0x9806,
1502 	0x9807,
1503 	0x9808,
1504 	0x9809,
1505 	0x980A,
1506 	0x9900,
1507 	0x9901,
1508 	0x9903,
1509 	0x9904,
1510 	0x9905,
1511 	0x9906,
1512 	0x9907,
1513 	0x9908,
1514 	0x9909,
1515 	0x990A,
1516 	0x990B,
1517 	0x990C,
1518 	0x990D,
1519 	0x990E,
1520 	0x990F,
1521 	0x9910,
1522 	0x9913,
1523 	0x9917,
1524 	0x9918,
1525 	0x9919,
1526 	0x9990,
1527 	0x9991,
1528 	0x9992,
1529 	0x9993,
1530 	0x9994,
1531 	0x9995,
1532 	0x9996,
1533 	0x9997,
1534 	0x9998,
1535 	0x9999,
1536 	0x999A,
1537 	0x999B,
1538 	0x999C,
1539 	0x999D,
1540 	0x99A0,
1541 	0x99A2,
1542 	0x99A4,
1544 	0x3171,
1545 	0x3e70,
1546 	0x4164,
1547 	0x4165,
1548 	0x4166,
1549 	0x4168,
1550 	0x4170,
1551 	0x4171,
1552 	0x4172,
1553 	0x4173,
1554 	0x496e,
1555 	0x4a69,
1556 	0x4a6a,
1557 	0x4a6b,
1558 	0x4a70,
1559 	0x4a74,
1560 	0x4b69,
1561 	0x4b6b,
1562 	0x4b6c,
1563 	0x4c6e,
1564 	0x4e64,
1565 	0x4e65,
1566 	0x4e66,
1567 	0x4e67,
1568 	0x4e68,
1569 	0x4e69,
1570 	0x4e6a,
1571 	0x4e71,
1572 	0x4f73,
1573 	0x5569,
1574 	0x556b,
1575 	0x556d,
1576 	0x556f,
1577 	0x5571,
1578 	0x5854,
1579 	0x5874,
1580 	0x5940,
1581 	0x5941,
1582 	0x5b72,
1583 	0x5b73,
1584 	0x5b74,
1585 	0x5b75,
1586 	0x5d44,
1587 	0x5d45,
1588 	0x5d6d,
1589 	0x5d6f,
1590 	0x5d72,
1591 	0x5d77,
1592 	0x5e6b,
1593 	0x5e6d,
1594 	0x7120,
1595 	0x7124,
1596 	0x7129,
1597 	0x712e,
1598 	0x712f,
1599 	0x7162,
1600 	0x7163,
1601 	0x7166,
1602 	0x7167,
1603 	0x7172,
1604 	0x7173,
1605 	0x71a0,
1606 	0x71a1,
1607 	0x71a3,
1608 	0x71a7,
1609 	0x71bb,
1610 	0x71e0,
1611 	0x71e1,
1612 	0x71e2,
1613 	0x71e6,
1614 	0x71e7,
1615 	0x71f2,
1616 	0x7269,
1617 	0x726b,
1618 	0x726e,
1619 	0x72a0,
1620 	0x72a8,
1621 	0x72b1,
1622 	0x72b3,
1623 	0x793f,
1628 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1629 	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1630 	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1631 	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1632 	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1633 	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1634 	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1635 	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1636 	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1637 	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1638 	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1639 	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1640 	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1641 	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1642 	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1643 	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1644 	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1645 	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1646 	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1647 	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1648 	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1649 	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1650 	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1651 	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1652 	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1653 	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1654 	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1655 	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1656 	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1657 	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1658 	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1659 	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1660 	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1661 	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1662 	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1663 	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1664 	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1665 	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1666 	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1667 	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1668 	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1669 	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1670 	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1671 	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1672 	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1673 	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1674 	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1675 	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1676 	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1677 	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1678 	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1679 	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1680 	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1681 	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1682 	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1683 	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1684 	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1685 	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1686 	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1687 	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1688 	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1689 	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1690 	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1691 	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1692 	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1693 	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1694 	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1695 	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1696 	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1697 	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1698 	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1699 	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1703 	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1704 	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1705 	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1706 	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1707 	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1708 	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1709 	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1710 	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1711 	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1712 	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1713 	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1714 	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1715 	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1716 	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1717 	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1718 	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1719 	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1720 	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1721 	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1722 	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1723 	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1724 	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1726 	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1727 	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1728 	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1729 	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1730 	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1731 	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1732 	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1733 	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1734 	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1735 	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1736 	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1738 	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1739 	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1740 	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1741 	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1742 	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1743 	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1744 	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1745 	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1746 	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1747 	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1748 	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1749 	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1751 	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1752 	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1753 	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1754 	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1755 	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1756 	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1757 	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1758 	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1759 	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1760 	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1761 	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1762 	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1763 	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1764 	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1765 	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1766 	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1768 	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1769 	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1770 	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1771 	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1772 	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1773 	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1774 	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1775 	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1776 	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1777 	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1778 	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1779 	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1780 	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1781 	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1782 	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1783 	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1786 	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1787 	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1788 	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1789 	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1790 	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1792 	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1793 	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1794 	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1795 	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1796 	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1797 	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1798 	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1799 	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1800 	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1802 	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1803 	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1805 	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1806 	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1807 	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1808 	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1809 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1811 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1813 	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1814 	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1815 	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1816 	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1817 	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1818 	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1819 	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1820 	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1821 	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1823 	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1824 	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1825 	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1826 	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1827 	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1828 	{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1829 	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1830 	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1831 	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1832 	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1833 	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1834 	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1835 	{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1837 	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1838 	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1839 	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1840 	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1841 	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1842 	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1843 	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1844 	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1846 	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1847 	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1848 	{0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1850 	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1851 	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1852 	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1853 	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1854 	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1855 	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1856 	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1857 	{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1858 	{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1859 	{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1860 	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1861 	{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1862 	{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1863 	{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1864 	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1866 	{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1867 	{0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1868 	{0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1869 	{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1870 	{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1872 	{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1873 	{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1874 	{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1875 	{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1876 	{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1877 	{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1878 	{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1880 	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1881 	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1883 	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1884 	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1885 	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1886 	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1888 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1889 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1890 	{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1891 	{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1892 	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1893 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1894 	{0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1895 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1897 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1898 	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1899 	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1900 	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1903 	{0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1904 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1905 	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1906 	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1909 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1910 	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1913 	{0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1914 	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1915 	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1916 	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1917 	{0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1918 	{0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1919 	{0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1920 	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1921 	{0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1922 	{0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1923 	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1924 	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1925 	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1928 	{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1931 	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1932 	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1935 	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1936 	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1937 	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1938 	{0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1939 	{0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1940 	{0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1941 	{0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1942 	{0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1943 	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1946 	{0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1947 	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1948 	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1949 	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1950 	{0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1951 	{0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1952 	{0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1953 	{0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1954 	{0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1955 	{0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1956 	{0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1957 	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1960 	{0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1961 	{0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1962 	{0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1963 	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1966 	{0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1967 	{0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1970 	{0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1971 	{0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1972 	{0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1973 	{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1974 	{0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1975 	{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1977 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
1979 	  .class_mask = 0xffffff,
1982 	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
1984 	  .class_mask = 0xffffff,
1987 	{0, 0, 0}
1999 	/* 0 - GPU  in amdgpu_get_secondary_funcs()
2022 	int ret, retry = 0, i;  in amdgpu_pci_probe()
2026 	for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {  in amdgpu_pci_probe()
2032 		amdgpu_aspm = 0;  in amdgpu_pci_probe()
2066 				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"  in amdgpu_pci_probe()
2083 				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"  in amdgpu_pci_probe()
2186 	return 0;  in amdgpu_pci_probe()
2204 	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&  in amdgpu_pci_remove()
2212 			if (hive->device_remove_count == 0)  in amdgpu_pci_remove()
2227 			memset(&reset_context, 0, sizeof(reset_context));  in amdgpu_pci_remove()
2281 	memset(&reset_context, 0, sizeof(reset_context));  in amdgpu_drv_delayed_reset_work_handler()
2295 	for (i = 0; i < mgpu_info.num_dgpu; i++) {  in amdgpu_drv_delayed_reset_work_handler()
2306 	for (i = 0; i < mgpu_info.num_dgpu; i++) {  in amdgpu_drv_delayed_reset_work_handler()
2313 	for (i = 0; i < mgpu_info.num_dgpu; i++)  in amdgpu_drv_delayed_reset_work_handler()
2318 	for (i = 0; i < mgpu_info.num_dgpu; i++)  in amdgpu_drv_delayed_reset_work_handler()
2333 	for (i = 0; i < mgpu_info.num_dgpu; i++) {  in amdgpu_drv_delayed_reset_work_handler()
2360 	return 0;  in amdgpu_pmops_prepare()
2388 	return 0;  in amdgpu_pmops_suspend_noirq()
2453 		int ret = 0;  in amdgpu_runtime_idle_check_display()
2482 				if (ret < 0)  in amdgpu_runtime_idle_check_display()
2506 	return 0;  in amdgpu_runtime_idle_check_display()
2526 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {  in amdgpu_pmops_runtime_suspend()
2575 	return 0;  in amdgpu_pmops_runtime_suspend()
2622 	return 0;  in amdgpu_pmops_runtime_resume()
2652 	if (ret < 0)  in amdgpu_drm_ioctl()
2687 	return timeout >= 0 ? 0 : timeout;  in amdgpu_flush()
2720 	return 0;  in amdgpu_file_to_fpriv()