48 					   struct amdgpu_framebuffer *rfb,
915 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,  in amdgpu_display_verify_plane()  argument
920 	unsigned int width = rfb->base.width /  in amdgpu_display_verify_plane()
922 	unsigned int height = rfb->base.height /  in amdgpu_display_verify_plane()
930 	if (rfb->base.pitches[plane] % block_pitch) {  in amdgpu_display_verify_plane()
931 		drm_dbg_kms(rfb->base.dev,  in amdgpu_display_verify_plane()
933 			    rfb->base.pitches[plane], plane, block_pitch);  in amdgpu_display_verify_plane()
936 	if (rfb->base.pitches[plane] < min_pitch) {  in amdgpu_display_verify_plane()
937 		drm_dbg_kms(rfb->base.dev,  in amdgpu_display_verify_plane()
939 			    rfb->base.pitches[plane], plane, min_pitch);  in amdgpu_display_verify_plane()
944 	if (rfb->base.offsets[plane] % block_size) {  in amdgpu_display_verify_plane()
945 		drm_dbg_kms(rfb->base.dev,  in amdgpu_display_verify_plane()
947 			    rfb->base.offsets[plane], plane, block_size);  in amdgpu_display_verify_plane()
951 	size = rfb->base.offsets[plane] +  in amdgpu_display_verify_plane()
952 		(uint64_t)rfb->base.pitches[plane] / block_pitch *  in amdgpu_display_verify_plane()
955 	if (rfb->base.obj[0]->size < size) {  in amdgpu_display_verify_plane()
956 		drm_dbg_kms(rfb->base.dev,  in amdgpu_display_verify_plane()
958 			    rfb->base.obj[0]->size, size, plane);  in amdgpu_display_verify_plane()
966 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)  in amdgpu_display_verify_sizes()  argument
968 	const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);  in amdgpu_display_verify_sizes()
969 	uint64_t modifier = rfb->base.modifier;  in amdgpu_display_verify_sizes()
973 	if (rfb->base.dev->mode_config.fb_modifiers_not_supported)  in amdgpu_display_verify_sizes()
1001 				drm_dbg_kms(rfb->base.dev,  in amdgpu_display_verify_sizes()
1010 		ret = amdgpu_display_verify_plane(rfb, i, format_info,  in amdgpu_display_verify_sizes()
1021 			ret = amdgpu_display_verify_plane(rfb, i, format_info,  in amdgpu_display_verify_sizes()
1036 		ret = amdgpu_display_verify_plane(rfb, i, format_info,  in amdgpu_display_verify_sizes()
1079 						 struct amdgpu_framebuffer *rfb,  in amdgpu_display_gem_fb_verify_and_init()  argument
1086 	rfb->base.obj[0] = obj;  in amdgpu_display_gem_fb_verify_and_init()
1087 	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);  in amdgpu_display_gem_fb_verify_and_init()
1099 	ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);  in amdgpu_display_gem_fb_verify_and_init()
1103 	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);  in amdgpu_display_gem_fb_verify_and_init()
1111 	rfb->base.obj[0] = NULL;  in amdgpu_display_gem_fb_verify_and_init()
1116 					   struct amdgpu_framebuffer *rfb,  in amdgpu_display_framebuffer_init()  argument
1127 	for (i = 1; i < rfb->base.format->num_planes; ++i) {  in amdgpu_display_framebuffer_init()
1136 	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);  in amdgpu_display_framebuffer_init()
1143 		ret = check_tiling_flags_gfx6(rfb);  in amdgpu_display_framebuffer_init()
1149 	    !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {  in amdgpu_display_framebuffer_init()
1150 		ret = convert_tiling_flags_to_modifier(rfb);  in amdgpu_display_framebuffer_init()
1153 				    rfb->tiling_flags);  in amdgpu_display_framebuffer_init()
1158 	ret = amdgpu_display_verify_sizes(rfb);  in amdgpu_display_framebuffer_init()
1162 	for (i = 0; i < rfb->base.format->num_planes; ++i) {  in amdgpu_display_framebuffer_init()
1163 		drm_gem_object_get(rfb->base.obj[0]);  in amdgpu_display_framebuffer_init()
1164 		rfb->base.obj[i] = rfb->base.obj[0];  in amdgpu_display_framebuffer_init()