596 amdgpu_lookup_format_info(u32 format, uint64_t modifier)  in amdgpu_lookup_format_info()  argument
598 	if (!IS_AMD_FMT_MOD(modifier))  in amdgpu_lookup_format_info()
601 	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))  in amdgpu_lookup_format_info()
606 	if (AMD_FMT_MOD_GET(DCC, modifier))  in amdgpu_lookup_format_info()
668 	uint64_t modifier = 0;  in convert_tiling_flags_to_modifier()  local
676 		modifier = DRM_FORMAT_MOD_LINEAR;  in convert_tiling_flags_to_modifier()
768 		modifier = AMD_FMT_MOD |  in convert_tiling_flags_to_modifier()
791 			modifier |= AMD_FMT_MOD_SET(DCC, 1) |  in convert_tiling_flags_to_modifier()
805 			 * but we should convert it to a modifier plane for getfb2, so the  in convert_tiling_flags_to_modifier()
816 				modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);  in convert_tiling_flags_to_modifier()
828 					modifier |= AMD_FMT_MOD_SET(RB, rb) |  in convert_tiling_flags_to_modifier()
838 								modifier);  in convert_tiling_flags_to_modifier()
846 	afb->base.modifier = modifier;  in convert_tiling_flags_to_modifier()
885 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,  in get_dcc_block_size()  argument
888 	unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);  in get_dcc_block_size()
897 		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);  in get_dcc_block_size()
902 		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);  in get_dcc_block_size()
905 		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)  in get_dcc_block_size()
969 	uint64_t modifier = rfb->base.modifier;  in amdgpu_display_verify_sizes()  local
977 		if (modifier == DRM_FORMAT_MOD_LINEAR) {  in amdgpu_display_verify_sizes()
982 			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);  in amdgpu_display_verify_sizes()
1016 	if (AMD_FMT_MOD_GET(DCC, modifier)) {  in amdgpu_display_verify_sizes()
1017 		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {  in amdgpu_display_verify_sizes()
1018 			block_size_log2 = get_dcc_block_size(modifier, false, false);  in amdgpu_display_verify_sizes()
1028 			block_size_log2 = get_dcc_block_size(modifier, true, true);  in amdgpu_display_verify_sizes()
1030 			bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);  in amdgpu_display_verify_sizes()
1032 			block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);  in amdgpu_display_verify_sizes()
1088 	/* Verify that the modifier is supported. */  in amdgpu_display_gem_fb_verify_and_init()
1090 				      mode_cmd->modifier[0])) {  in amdgpu_display_gem_fb_verify_and_init()
1092 			    "unsupported pixel format %p4cc / modifier 0x%llx\n",  in amdgpu_display_gem_fb_verify_and_init()
1093 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);  in amdgpu_display_gem_fb_verify_and_init()
1124 	 * This needs to happen before modifier conversion as that might change  in amdgpu_display_framebuffer_init()
1142 			      "GFX9+ requires FB check based on format modifier\n");  in amdgpu_display_framebuffer_init()
1152 			drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",  in amdgpu_display_framebuffer_init()