Lines Matching defs:amdgpu_device
757 struct amdgpu_device { struct
758 struct device *dev;
759 struct pci_dev *pdev;
760 struct drm_device ddev;
763 struct amdgpu_acp acp;
765 struct amdgpu_hive_info *hive;
767 enum amd_asic_type asic_type;
768 uint32_t family;
769 uint32_t rev_id;
770 uint32_t external_rev_id;
771 unsigned long flags;
772 unsigned long apu_flags;
773 int usec_timeout;
774 const struct amdgpu_asic_funcs *asic_funcs;
775 bool shutdown;
776 bool need_swiotlb;
777 bool accel_working;
778 struct notifier_block acpi_nb;
779 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
780 struct debugfs_blob_wrapper debugfs_vbios_blob;
781 struct debugfs_blob_wrapper debugfs_discovery_blob;
782 struct mutex srbm_mutex;
784 struct mutex grbm_idx_mutex;
785 struct dev_pm_domain vga_pm_domain;
786 bool have_disp_power_ref;
787 bool have_atomics_support;
790 bool is_atom_fw;
791 uint8_t *bios;
792 uint32_t bios_size;
793 uint32_t bios_scratch_reg_offset;
794 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
797 resource_size_t rmmio_base;
798 resource_size_t rmmio_size;
799 void __iomem *rmmio;
801 spinlock_t mmio_idx_lock;
802 struct amdgpu_mmio_remap rmmio_remap;
804 spinlock_t smc_idx_lock;
805 amdgpu_rreg_t smc_rreg;
806 amdgpu_wreg_t smc_wreg;
808 spinlock_t pcie_idx_lock;
809 amdgpu_rreg_t pcie_rreg;
810 amdgpu_wreg_t pcie_wreg;
811 amdgpu_rreg_t pciep_rreg;
812 amdgpu_wreg_t pciep_wreg;
813 amdgpu_rreg64_t pcie_rreg64;
814 amdgpu_wreg64_t pcie_wreg64;
816 spinlock_t uvd_ctx_idx_lock;
817 amdgpu_rreg_t uvd_ctx_rreg;
818 amdgpu_wreg_t uvd_ctx_wreg;
820 spinlock_t didt_idx_lock;
821 amdgpu_rreg_t didt_rreg;
822 amdgpu_wreg_t didt_wreg;
824 spinlock_t gc_cac_idx_lock;
825 amdgpu_rreg_t gc_cac_rreg;
826 amdgpu_wreg_t gc_cac_wreg;
828 spinlock_t se_cac_idx_lock;
829 amdgpu_rreg_t se_cac_rreg;
830 amdgpu_wreg_t se_cac_wreg;
832 spinlock_t audio_endpt_idx_lock;
833 amdgpu_block_rreg_t audio_endpt_rreg;
834 amdgpu_block_wreg_t audio_endpt_wreg;
835 struct amdgpu_doorbell doorbell;
838 struct amdgpu_clock clock;
841 struct amdgpu_gmc gmc;
842 struct amdgpu_gart gart;
843 dma_addr_t dummy_page_addr;
844 struct amdgpu_vm_manager vm_manager;
845 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
846 unsigned num_vmhubs;
871 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ argument
872 struct work_struct hotplug_work;
873 struct amdgpu_irq_src crtc_irq;
874 struct amdgpu_irq_src vline0_irq;
875 struct amdgpu_irq_src vupdate_irq;
876 struct amdgpu_irq_src pageflip_irq;
877 struct amdgpu_irq_src hpd_irq;
878 struct amdgpu_irq_src dmub_trace_irq;
879 struct amdgpu_irq_src dmub_outbox_irq;
882 u64 fence_context;
883 unsigned num_rings;
884 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
885 struct dma_fence __rcu *gang_submit;
886 bool ib_pool_ready;
887 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
888 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
891 struct amdgpu_irq irq;
894 struct amd_powerplay powerplay;
895 struct amdgpu_pm pm;
896 u64 cg_flags;
897 u32 pg_flags;
900 struct amdgpu_nbio nbio;
903 struct amdgpu_hdp hdp;
906 struct amdgpu_smuio smuio;
909 struct amdgpu_mmhub mmhub;
912 struct amdgpu_gfxhub gfxhub;
915 struct amdgpu_gfx gfx;
918 struct amdgpu_sdma sdma;
921 struct amdgpu_lsdma lsdma;
924 struct amdgpu_uvd uvd;
927 struct amdgpu_vce vce;
930 struct amdgpu_vcn vcn;
933 struct amdgpu_jpeg jpeg;
936 struct amdgpu_firmware firmware;
939 struct psp_context psp;
942 struct amdgpu_gds gds;
945 struct amdgpu_kfd_dev kfd;
948 struct amdgpu_umc umc;
951 struct amdgpu_display_manager dm;
954 bool enable_mes;
955 bool enable_mes_kiq;
956 struct amdgpu_mes mes;
957 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
960 struct amdgpu_df df;
963 struct amdgpu_mca mca;
965 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
966 uint32_t harvest_ip_mask;
967 int num_ip_blocks;
968 struct mutex mn_lock;
972 atomic64_t vram_pin_size;
973 atomic64_t visible_pin_size;
974 atomic64_t gart_pin_size;
977 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
980 struct delayed_work delayed_init_work;
982 struct amdgpu_virt virt;
985 struct list_head shadow_list;
986 struct mutex shadow_list_lock;
989 bool has_hw_reset;
990 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
993 bool in_suspend;
994 bool in_s3;
995 bool in_s4;
996 bool in_s0ix;
998 enum pp_mp1_state mp1_state;
999 struct amdgpu_doorbell_index doorbell_index;
1001 struct mutex notifier_lock;
1003 int asic_reset_res;
1004 struct work_struct xgmi_reset_work;
1005 struct list_head reset_list;
1007 long gfx_timeout;
1008 long sdma_timeout;
1009 long video_timeout;
1010 long compute_timeout;
1012 uint64_t unique_id;
1013 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1016 bool in_runpm;
1017 bool has_pr3;
1019 bool pm_sysfs_en;
1020 bool ucode_sysfs_en;
1021 bool psp_sysfs_en;
1024 char product_number[20];
1025 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1026 char serial[20];
1028 atomic_t throttling_logging_enabled;
1029 struct ratelimit_state throttling_logging_rs;
1030 uint32_t ras_hw_enabled;
1031 uint32_t ras_enabled;
1033 bool no_hw_access;
1034 struct pci_saved_state *pci_state;
1035 pci_channel_state_t pci_channel_state;
1037 struct amdgpu_reset_control *reset_cntl;
1038 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1040 bool ram_is_direct_mapped;
1042 struct list_head ras_list;
1044 struct ip_discovery_top *ip_top;
1068 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) in drm_to_adev() argument