1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2008 - 2013 Xilinx, Inc.
31 #define XGPIO_GIER_IE		BIT(31)
45  * struct xgpio_instance - Stores information about GPIO device
64 	DECLARE_BITMAP(hw_map, 64);
65 	DECLARE_BITMAP(sw_map, 64);
66 	DECLARE_BITMAP(state, 64);
67 	DECLARE_BITMAP(last_irq_read, 64);
68 	DECLARE_BITMAP(dir, 64);
72 	DECLARE_BITMAP(enable, 64);
73 	DECLARE_BITMAP(rising_edge, 64);
74 	DECLARE_BITMAP(falling_edge, 64);
78 static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)  in xgpio_from_bit()  argument
80 	return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);  in xgpio_from_bit()
85 	return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);  in xgpio_to_bit()
88 static inline u32 xgpio_get_value32(const unsigned long *map, int bit)  in xgpio_get_value32()  argument
90 	const size_t index = BIT_WORD(bit);  in xgpio_get_value32()
91 	const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);  in xgpio_get_value32()
96 static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)  in xgpio_set_value32()  argument
98 	const size_t index = BIT_WORD(bit);  in xgpio_set_value32()
99 	const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);  in xgpio_set_value32()
113 		return -EINVAL;  in xgpio_regoffset()
117 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)  in xgpio_read_ch()  argument
119 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);  in xgpio_read_ch()
121 	xgpio_set_value32(a, bit, xgpio_readreg(addr));  in xgpio_read_ch()
124 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)  in xgpio_write_ch()  argument
126 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);  in xgpio_write_ch()
128 	xgpio_writereg(addr, xgpio_get_value32(a, bit));  in xgpio_write_ch()
133 	int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);  in xgpio_read_ch_all()  local
135 	for (bit = 0; bit <= lastbit ; bit += 32)  in xgpio_read_ch_all()
136 		xgpio_read_ch(chip, reg, bit, a);  in xgpio_read_ch_all()
141 	int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);  in xgpio_write_ch_all()  local
143 	for (bit = 0; bit <= lastbit ; bit += 32)  in xgpio_write_ch_all()
144 		xgpio_write_ch(chip, reg, bit, a);  in xgpio_write_ch_all()
148  * xgpio_get - Read the specified signal of the GPIO device.
161 	int bit = xgpio_to_bit(chip, gpio);  in xgpio_get()  local
162 	DECLARE_BITMAP(state, 64);  in xgpio_get()
164 	xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);  in xgpio_get()
166 	return test_bit(bit, state);  in xgpio_get()
170  * xgpio_set - Write the specified signal of the GPIO device.
182 	int bit = xgpio_to_bit(chip, gpio);  in xgpio_set()  local
184 	spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_set()
187 	__assign_bit(bit, chip->state, val);  in xgpio_set()
189 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);  in xgpio_set()
191 	spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_set()
195  * xgpio_set_multiple - Write the specified signals of the GPIO device.
206 	DECLARE_BITMAP(hw_mask, 64);  in xgpio_set_multiple()
207 	DECLARE_BITMAP(hw_bits, 64);  in xgpio_set_multiple()
208 	DECLARE_BITMAP(state, 64);  in xgpio_set_multiple()
212 	bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);  in xgpio_set_multiple()
213 	bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);  in xgpio_set_multiple()
215 	spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_set_multiple()
217 	bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);  in xgpio_set_multiple()
221 	bitmap_copy(chip->state, state, 64);  in xgpio_set_multiple()
223 	spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_set_multiple()
227  * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
232  * 0 - if direction of GPIO signals is set as input
239 	int bit = xgpio_to_bit(chip, gpio);  in xgpio_dir_in()  local
241 	spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_dir_in()
243 	/* Set the GPIO bit in shadow register and set direction as input */  in xgpio_dir_in()
244 	__set_bit(bit, chip->dir);  in xgpio_dir_in()
245 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);  in xgpio_dir_in()
247 	spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_dir_in()
253  * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
268 	int bit = xgpio_to_bit(chip, gpio);  in xgpio_dir_out()  local
270 	spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_dir_out()
273 	__assign_bit(bit, chip->state, val);  in xgpio_dir_out()
274 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);  in xgpio_dir_out()
276 	/* Clear the GPIO bit in shadow register and set direction as output */  in xgpio_dir_out()
277 	__clear_bit(bit, chip->dir);  in xgpio_dir_out()
278 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);  in xgpio_dir_out()
280 	spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_dir_out()
286  * xgpio_save_regs - Set initial values of GPIO pins
291 	xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);  in xgpio_save_regs()
292 	xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);  in xgpio_save_regs()
299 	ret = pm_runtime_get_sync(chip->parent);  in xgpio_request()
309 	pm_runtime_put(chip->parent);  in xgpio_free()
315 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in xgpio_suspend()
329  * xgpio_remove - Remove method for the GPIO device.
340 	pm_runtime_get_sync(&pdev->dev);  in xgpio_remove()
341 	pm_runtime_put_noidle(&pdev->dev);  in xgpio_remove()
342 	pm_runtime_disable(&pdev->dev);  in xgpio_remove()
343 	clk_disable_unprepare(gpio->clk);  in xgpio_remove()
349  * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
361 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in xgpio_resume()
378 	clk_disable(gpio->clk);  in xgpio_runtime_suspend()
387 	return clk_enable(gpio->clk);  in xgpio_runtime_resume()
397  * xgpio_irq_mask - Write the specified signal of the GPIO device.
405 	int bit = xgpio_to_bit(chip, irq_offset);  in xgpio_irq_mask()  local
406 	u32 mask = BIT(bit / 32), temp;  in xgpio_irq_mask()
408 	spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_irq_mask()
410 	__clear_bit(bit, chip->enable);  in xgpio_irq_mask()
412 	if (xgpio_get_value32(chip->enable, bit) == 0) {  in xgpio_irq_mask()
414 		temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);  in xgpio_irq_mask()
416 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);  in xgpio_irq_mask()
418 	spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_irq_mask()
422  * xgpio_irq_unmask - Write the specified signal of the GPIO device.
430 	int bit = xgpio_to_bit(chip, irq_offset);  in xgpio_irq_unmask()  local
431 	u32 old_enable = xgpio_get_value32(chip->enable, bit);  in xgpio_irq_unmask()
432 	u32 mask = BIT(bit / 32), val;  in xgpio_irq_unmask()
434 	spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_irq_unmask()
436 	__set_bit(bit, chip->enable);  in xgpio_irq_unmask()
439 		/* Clear any existing per-channel interrupts */  in xgpio_irq_unmask()
440 		val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_irq_unmask()
442 		xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);  in xgpio_irq_unmask()
445 		xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);  in xgpio_irq_unmask()
448 		val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);  in xgpio_irq_unmask()
450 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);  in xgpio_irq_unmask()
453 	spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_irq_unmask()
457  * xgpio_set_irq_type - Write the specified signal of the GPIO device.
462  * 0 if interrupt type is supported otherwise -EINVAL
468 	int bit = xgpio_to_bit(chip, irq_offset);  in xgpio_set_irq_type()  local
478 		__set_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
479 		__set_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
482 		__set_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
483 		__clear_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
486 		__clear_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
487 		__set_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
490 		return -EINVAL;  in xgpio_set_irq_type()
498  * xgpio_irqhandler - Gpio interrupt service routine
504 	struct gpio_chip *gc = &chip->gc;  in xgpio_irqhandler()
506 	DECLARE_BITMAP(rising, 64);  in xgpio_irqhandler()
507 	DECLARE_BITMAP(falling, 64);  in xgpio_irqhandler()
508 	DECLARE_BITMAP(all, 64);  in xgpio_irqhandler()
511 	u32 bit;  in xgpio_irqhandler()  local
513 	status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_irqhandler()
514 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);  in xgpio_irqhandler()
518 	spin_lock(&chip->gpio_lock);  in xgpio_irqhandler()
522 	bitmap_complement(rising, chip->last_irq_read, 64);  in xgpio_irqhandler()
523 	bitmap_and(rising, rising, all, 64);  in xgpio_irqhandler()
524 	bitmap_and(rising, rising, chip->enable, 64);  in xgpio_irqhandler()
525 	bitmap_and(rising, rising, chip->rising_edge, 64);  in xgpio_irqhandler()
527 	bitmap_complement(falling, all, 64);  in xgpio_irqhandler()
528 	bitmap_and(falling, falling, chip->last_irq_read, 64);  in xgpio_irqhandler()
529 	bitmap_and(falling, falling, chip->enable, 64);  in xgpio_irqhandler()
530 	bitmap_and(falling, falling, chip->falling_edge, 64);  in xgpio_irqhandler()
532 	bitmap_copy(chip->last_irq_read, all, 64);  in xgpio_irqhandler()
533 	bitmap_or(all, rising, falling, 64);  in xgpio_irqhandler()
535 	spin_unlock(&chip->gpio_lock);  in xgpio_irqhandler()
537 	dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);  in xgpio_irqhandler()
539 	for_each_set_bit(bit, all, 64) {  in xgpio_irqhandler()
540 		irq_offset = xgpio_from_bit(chip, bit);  in xgpio_irqhandler()
541 		generic_handle_domain_irq(gc->irq.domain, irq_offset);  in xgpio_irqhandler()
548  * xgpio_probe - Probe method for the GPIO device.
559 	struct device_node *np = pdev->dev.of_node;  in xgpio_probe()
568 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);  in xgpio_probe()
570 		return -ENOMEM;  in xgpio_probe()
574 	/* First, check if the device is dual-channel */  in xgpio_probe()
575 	of_property_read_u32(np, "xlnx,is-dual", &is_dual);  in xgpio_probe()
583 	of_property_read_u32(np, "xlnx,dout-default", &state[0]);  in xgpio_probe()
584 	of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);  in xgpio_probe()
586 	bitmap_from_arr32(chip->state, state, 64);  in xgpio_probe()
589 	of_property_read_u32(np, "xlnx,tri-default", &dir[0]);  in xgpio_probe()
590 	of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);  in xgpio_probe()
592 	bitmap_from_arr32(chip->dir, dir, 64);  in xgpio_probe()
594 	/* Update cells with gpio-cells value */  in xgpio_probe()
595 	if (of_property_read_u32(np, "#gpio-cells", &cells))  in xgpio_probe()
596 		dev_dbg(&pdev->dev, "Missing gpio-cells property\n");  in xgpio_probe()
599 		dev_err(&pdev->dev, "#gpio-cells mismatch\n");  in xgpio_probe()
600 		return -EINVAL;  in xgpio_probe()
607 	if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))  in xgpio_probe()
611 		return -EINVAL;  in xgpio_probe()
613 	if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))  in xgpio_probe()
617 		return -EINVAL;  in xgpio_probe()
620 	bitmap_set(chip->sw_map, 0, width[0] + width[1]);  in xgpio_probe()
623 	bitmap_set(chip->hw_map,  0, width[0]);  in xgpio_probe()
624 	bitmap_set(chip->hw_map, 32, width[1]);  in xgpio_probe()
626 	spin_lock_init(&chip->gpio_lock);  in xgpio_probe()
628 	chip->gc.base = -1;  in xgpio_probe()
629 	chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);  in xgpio_probe()
630 	chip->gc.parent = &pdev->dev;  in xgpio_probe()
631 	chip->gc.direction_input = xgpio_dir_in;  in xgpio_probe()
632 	chip->gc.direction_output = xgpio_dir_out;  in xgpio_probe()
633 	chip->gc.of_gpio_n_cells = cells;  in xgpio_probe()
634 	chip->gc.get = xgpio_get;  in xgpio_probe()
635 	chip->gc.set = xgpio_set;  in xgpio_probe()
636 	chip->gc.request = xgpio_request;  in xgpio_probe()
637 	chip->gc.free = xgpio_free;  in xgpio_probe()
638 	chip->gc.set_multiple = xgpio_set_multiple;  in xgpio_probe()
640 	chip->gc.label = dev_name(&pdev->dev);  in xgpio_probe()
642 	chip->regs = devm_platform_ioremap_resource(pdev, 0);  in xgpio_probe()
643 	if (IS_ERR(chip->regs)) {  in xgpio_probe()
644 		dev_err(&pdev->dev, "failed to ioremap memory resource\n");  in xgpio_probe()
645 		return PTR_ERR(chip->regs);  in xgpio_probe()
648 	chip->clk = devm_clk_get_optional(&pdev->dev, NULL);  in xgpio_probe()
649 	if (IS_ERR(chip->clk))  in xgpio_probe()
650 		return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");  in xgpio_probe()
652 	status = clk_prepare_enable(chip->clk);  in xgpio_probe()
654 		dev_err(&pdev->dev, "Failed to prepare clk\n");  in xgpio_probe()
657 	pm_runtime_get_noresume(&pdev->dev);  in xgpio_probe()
658 	pm_runtime_set_active(&pdev->dev);  in xgpio_probe()
659 	pm_runtime_enable(&pdev->dev);  in xgpio_probe()
663 	chip->irq = platform_get_irq_optional(pdev, 0);  in xgpio_probe()
664 	if (chip->irq <= 0)  in xgpio_probe()
667 	chip->irqchip.name = "gpio-xilinx";  in xgpio_probe()
668 	chip->irqchip.irq_ack = xgpio_irq_ack;  in xgpio_probe()
669 	chip->irqchip.irq_mask = xgpio_irq_mask;  in xgpio_probe()
670 	chip->irqchip.irq_unmask = xgpio_irq_unmask;  in xgpio_probe()
671 	chip->irqchip.irq_set_type = xgpio_set_irq_type;  in xgpio_probe()
673 	/* Disable per-channel interrupts */  in xgpio_probe()
674 	xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);  in xgpio_probe()
675 	/* Clear any existing per-channel interrupts */  in xgpio_probe()
676 	temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_probe()
677 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);  in xgpio_probe()
679 	xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);  in xgpio_probe()
681 	girq = &chip->gc.irq;  in xgpio_probe()
682 	girq->chip = &chip->irqchip;  in xgpio_probe()
683 	girq->parent_handler = xgpio_irqhandler;  in xgpio_probe()
684 	girq->num_parents = 1;  in xgpio_probe()
685 	girq->parents = devm_kcalloc(&pdev->dev, 1,  in xgpio_probe()
686 				     sizeof(*girq->parents),  in xgpio_probe()
688 	if (!girq->parents) {  in xgpio_probe()
689 		status = -ENOMEM;  in xgpio_probe()
692 	girq->parents[0] = chip->irq;  in xgpio_probe()
693 	girq->default_type = IRQ_TYPE_NONE;  in xgpio_probe()
694 	girq->handler = handle_bad_irq;  in xgpio_probe()
697 	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);  in xgpio_probe()
699 		dev_err(&pdev->dev, "failed to add GPIO chip\n");  in xgpio_probe()
703 	pm_runtime_put(&pdev->dev);  in xgpio_probe()
707 	pm_runtime_disable(&pdev->dev);  in xgpio_probe()
708 	pm_runtime_put_noidle(&pdev->dev);  in xgpio_probe()
709 	clk_disable_unprepare(chip->clk);  in xgpio_probe()
714 	{ .compatible = "xlnx,xps-gpio-1.00.a", },
724 			.name = "gpio-xilinx",