70 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)  in gpio_rcar_read()  argument
72 	return ioread32(p->base + offs);  in gpio_rcar_read()
75 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,  in gpio_rcar_write()  argument
78 	iowrite32(value, p->base + offs);  in gpio_rcar_write()
81 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,  in gpio_rcar_modify_bit()  argument
84 	u32 tmp = gpio_rcar_read(p, offs);  in gpio_rcar_modify_bit()
91 	gpio_rcar_write(p, offs, tmp);  in gpio_rcar_modify_bit()
97 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);  in gpio_rcar_irq_disable()  local
100 	gpio_rcar_write(p, INTMSK, ~BIT(hwirq));  in gpio_rcar_irq_disable()
107 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);  in gpio_rcar_irq_enable()  local
111 	gpio_rcar_write(p, MSKCLR, BIT(hwirq));  in gpio_rcar_irq_enable()
114 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,  in gpio_rcar_config_interrupt_input_mode()  argument
127 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_config_interrupt_input_mode()
130 	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);  in gpio_rcar_config_interrupt_input_mode()
133 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);  in gpio_rcar_config_interrupt_input_mode()
136 	if (p->info.has_both_edge_trigger)  in gpio_rcar_config_interrupt_input_mode()
137 		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);  in gpio_rcar_config_interrupt_input_mode()
140 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);  in gpio_rcar_config_interrupt_input_mode()
144 		gpio_rcar_write(p, INTCLR, BIT(hwirq));  in gpio_rcar_config_interrupt_input_mode()
146 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_config_interrupt_input_mode()
152 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);  in gpio_rcar_irq_set_type()  local
155 	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);  in gpio_rcar_irq_set_type()
159 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,  in gpio_rcar_irq_set_type()
163 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,  in gpio_rcar_irq_set_type()
167 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,  in gpio_rcar_irq_set_type()
171 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,  in gpio_rcar_irq_set_type()
175 		if (!p->info.has_both_edge_trigger)  in gpio_rcar_irq_set_type()
177 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,  in gpio_rcar_irq_set_type()
189 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);  in gpio_rcar_irq_set_wake()  local
192 	if (p->irq_parent) {  in gpio_rcar_irq_set_wake()
193 		error = irq_set_irq_wake(p->irq_parent, on);  in gpio_rcar_irq_set_wake()
195 			dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",  in gpio_rcar_irq_set_wake()
196 				p->irq_parent);  in gpio_rcar_irq_set_wake()
197 			p->irq_parent = 0;  in gpio_rcar_irq_set_wake()
202 		atomic_inc(&p->wakeup_path);  in gpio_rcar_irq_set_wake()
204 		atomic_dec(&p->wakeup_path);  in gpio_rcar_irq_set_wake()
222 	struct gpio_rcar_priv *p = dev_id;  in gpio_rcar_irq_handler()  local
226 	while ((pending = gpio_rcar_read(p, INTDT) &  in gpio_rcar_irq_handler()
227 			  gpio_rcar_read(p, INTMSK))) {  in gpio_rcar_irq_handler()
229 		gpio_rcar_write(p, INTCLR, BIT(offset));  in gpio_rcar_irq_handler()
230 		generic_handle_domain_irq(p->gpio_chip.irq.domain,  in gpio_rcar_irq_handler()
242 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_config_general_input_output_mode()  local
250 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_config_general_input_output_mode()
253 	gpio_rcar_modify_bit(p, POSNEG, gpio, false);  in gpio_rcar_config_general_input_output_mode()
256 	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);  in gpio_rcar_config_general_input_output_mode()
259 	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);  in gpio_rcar_config_general_input_output_mode()
262 	if (p->info.has_outdtsel && output)  in gpio_rcar_config_general_input_output_mode()
263 		gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);  in gpio_rcar_config_general_input_output_mode()
265 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_config_general_input_output_mode()
270 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_request()  local
273 	error = pm_runtime_get_sync(p->dev);  in gpio_rcar_request()
275 		pm_runtime_put(p->dev);  in gpio_rcar_request()
281 		pm_runtime_put(p->dev);  in gpio_rcar_request()
288 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_free()  local
298 	pm_runtime_put(p->dev);  in gpio_rcar_free()
303 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_get_direction()  local
305 	if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))  in gpio_rcar_get_direction()
319 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_get()  local
326 	if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))  in gpio_rcar_get()
327 		return !!(gpio_rcar_read(p, OUTDT) & bit);  in gpio_rcar_get()
329 		return !!(gpio_rcar_read(p, INDT) & bit);  in gpio_rcar_get()
335 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_get_multiple()  local
346 	if (p->info.has_always_in) {  in gpio_rcar_get_multiple()
347 		bits[0] = gpio_rcar_read(p, INDT) & bankmask;  in gpio_rcar_get_multiple()
351 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_get_multiple()
352 	outputs = gpio_rcar_read(p, INOUTSEL);  in gpio_rcar_get_multiple()
355 		val |= gpio_rcar_read(p, OUTDT) & m;  in gpio_rcar_get_multiple()
359 		val |= gpio_rcar_read(p, INDT) & m;  in gpio_rcar_get_multiple()
360 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_get_multiple()
368 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_set()  local
371 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_set()
372 	gpio_rcar_modify_bit(p, OUTDT, offset, value);  in gpio_rcar_set()
373 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_set()
379 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);  in gpio_rcar_set_multiple()  local
390 	spin_lock_irqsave(&p->lock, flags);  in gpio_rcar_set_multiple()
391 	val = gpio_rcar_read(p, OUTDT);  in gpio_rcar_set_multiple()
394 	gpio_rcar_write(p, OUTDT, val);  in gpio_rcar_set_multiple()
395 	spin_unlock_irqrestore(&p->lock, flags);  in gpio_rcar_set_multiple()
461 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)  in gpio_rcar_parse_dt()  argument
463 	struct device_node *np = p->dev->of_node;  in gpio_rcar_parse_dt()
468 	info = of_device_get_match_data(p->dev);  in gpio_rcar_parse_dt()
469 	p->info = *info;  in gpio_rcar_parse_dt()
475 		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",  in gpio_rcar_parse_dt()
483 static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)  in gpio_rcar_enable_inputs()  argument
485 	u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);  in gpio_rcar_enable_inputs()
488 	if (p->gpio_chip.valid_mask)  in gpio_rcar_enable_inputs()
489 		mask &= p->gpio_chip.valid_mask[0];  in gpio_rcar_enable_inputs()
491 		gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);  in gpio_rcar_enable_inputs()
496 	struct gpio_rcar_priv *p;  in gpio_rcar_probe()  local
504 	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);  in gpio_rcar_probe()
505 	if (!p)  in gpio_rcar_probe()
508 	p->dev = dev;  in gpio_rcar_probe()
509 	spin_lock_init(&p->lock);  in gpio_rcar_probe()
512 	ret = gpio_rcar_parse_dt(p, &npins);  in gpio_rcar_probe()
516 	platform_set_drvdata(pdev, p);  in gpio_rcar_probe()
523 	p->irq_parent = ret;  in gpio_rcar_probe()
525 	p->base = devm_platform_ioremap_resource(pdev, 0);  in gpio_rcar_probe()
526 	if (IS_ERR(p->base)) {  in gpio_rcar_probe()
527 		ret = PTR_ERR(p->base);  in gpio_rcar_probe()
531 	gpio_chip = &p->gpio_chip;  in gpio_rcar_probe()
556 	ret = gpiochip_add_data(gpio_chip, p);  in gpio_rcar_probe()
563 	ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,  in gpio_rcar_probe()
564 			       IRQF_SHARED, name, p);  in gpio_rcar_probe()
570 	if (p->info.has_inen) {  in gpio_rcar_probe()
572 		gpio_rcar_enable_inputs(p);  in gpio_rcar_probe()
589 	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);  in gpio_rcar_remove()  local
591 	gpiochip_remove(&p->gpio_chip);  in gpio_rcar_remove()
600 	struct gpio_rcar_priv *p = dev_get_drvdata(dev);  in gpio_rcar_suspend()  local
602 	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);  in gpio_rcar_suspend()
603 	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);  in gpio_rcar_suspend()
604 	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);  in gpio_rcar_suspend()
605 	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);  in gpio_rcar_suspend()
606 	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);  in gpio_rcar_suspend()
607 	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);  in gpio_rcar_suspend()
608 	if (p->info.has_both_edge_trigger)  in gpio_rcar_suspend()
609 		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);  in gpio_rcar_suspend()
611 	if (atomic_read(&p->wakeup_path))  in gpio_rcar_suspend()
619 	struct gpio_rcar_priv *p = dev_get_drvdata(dev);  in gpio_rcar_resume()  local
623 	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {  in gpio_rcar_resume()
624 		if (!gpiochip_line_is_valid(&p->gpio_chip, offset))  in gpio_rcar_resume()
629 		if (!(p->bank_info.iointsel & mask)) {  in gpio_rcar_resume()
630 			if (p->bank_info.inoutsel & mask)  in gpio_rcar_resume()
632 					&p->gpio_chip, offset,  in gpio_rcar_resume()
633 					!!(p->bank_info.outdt & mask));  in gpio_rcar_resume()
635 				gpio_rcar_direction_input(&p->gpio_chip,  in gpio_rcar_resume()
640 				p,  in gpio_rcar_resume()
642 				!(p->bank_info.posneg & mask),  in gpio_rcar_resume()
643 				!(p->bank_info.edglevel & mask),  in gpio_rcar_resume()
644 				!!(p->bank_info.bothedge & mask));  in gpio_rcar_resume()
646 			if (p->bank_info.intmsk & mask)  in gpio_rcar_resume()
647 				gpio_rcar_write(p, MSKCLR, mask);  in gpio_rcar_resume()
651 	if (p->info.has_inen)  in gpio_rcar_resume()
652 		gpio_rcar_enable_inputs(p);  in gpio_rcar_resume()