Lines Matching +full:mmp2 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-pxa/gpio.c
15 #include <linux/gpio-pxa.h>
34 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
35 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
36 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
38 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
39 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
40 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
42 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
151 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
163 struct pxa_gpio_bank *bank = p->banks + (gpio / 32); in gpio_bank_base()
165 return bank->regbase; in gpio_bank_base()
171 return chip_to_pxachip(c)->banks + gpio / 32; in gpio_to_pxabank()
198 * accurate, you are welcome to propose a better one :-)
206 base = gpio_bank_base(&pchip->chip, gpio); in __gpio_is_occupied()
234 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); in pxa_irq_to_gpio()
236 return irq - irq_gpio0; in pxa_irq_to_gpio()
257 return irq_find_mapping(pchip->irqdomain, offset); in pxa_gpio_to_irq()
268 ret = pinctrl_gpio_direction_input(chip->base + offset); in pxa_gpio_direction_input()
276 if (__gpio_is_inverted(chip->base + offset)) in pxa_gpio_direction_input()
297 ret = pinctrl_gpio_direction_output(chip->base + offset); in pxa_gpio_direction_output()
305 if (__gpio_is_inverted(chip->base + offset)) in pxa_gpio_direction_output()
336 if (gpiospec->args[0] > pxa_last_gpio) in pxa_gpio_of_xlate()
337 return -EINVAL; in pxa_gpio_of_xlate()
340 *flags = gpiospec->args[1]; in pxa_gpio_of_xlate()
342 return gpiospec->args[0]; in pxa_gpio_of_xlate()
351 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), in pxa_init_gpio_chip()
353 if (!pchip->banks) in pxa_init_gpio_chip()
354 return -ENOMEM; in pxa_init_gpio_chip()
356 pchip->chip.parent = pchip->dev; in pxa_init_gpio_chip()
357 pchip->chip.label = "gpio-pxa"; in pxa_init_gpio_chip()
358 pchip->chip.direction_input = pxa_gpio_direction_input; in pxa_init_gpio_chip()
359 pchip->chip.direction_output = pxa_gpio_direction_output; in pxa_init_gpio_chip()
360 pchip->chip.get = pxa_gpio_get; in pxa_init_gpio_chip()
361 pchip->chip.set = pxa_gpio_set; in pxa_init_gpio_chip()
362 pchip->chip.to_irq = pxa_gpio_to_irq; in pxa_init_gpio_chip()
363 pchip->chip.ngpio = ngpio; in pxa_init_gpio_chip()
364 pchip->chip.request = gpiochip_generic_request; in pxa_init_gpio_chip()
365 pchip->chip.free = gpiochip_generic_free; in pxa_init_gpio_chip()
368 pchip->chip.of_xlate = pxa_gpio_of_xlate; in pxa_init_gpio_chip()
369 pchip->chip.of_gpio_n_cells = 2; in pxa_init_gpio_chip()
373 bank = pchip->banks + i; in pxa_init_gpio_chip()
374 bank->regbase = regbase + BANK_OFF(i); in pxa_init_gpio_chip()
377 return gpiochip_add_data(&pchip->chip, pchip); in pxa_init_gpio_chip()
381 * bits are set in c->irq_mask
387 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
388 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
389 grer |= c->irq_edge_rise & c->irq_mask; in update_edge_detect()
390 gfer |= c->irq_edge_fall & c->irq_mask; in update_edge_detect()
391 writel_relaxed(grer, c->regbase + GRER_OFFSET); in update_edge_detect()
392 writel_relaxed(gfer, c->regbase + GFER_OFFSET); in update_edge_detect()
399 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); in pxa_gpio_irq_type()
406 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) in pxa_gpio_irq_type()
415 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
418 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
420 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
423 c->irq_edge_rise |= mask; in pxa_gpio_irq_type()
425 c->irq_edge_rise &= ~mask; in pxa_gpio_irq_type()
428 c->irq_edge_fall |= mask; in pxa_gpio_irq_type()
430 c->irq_edge_fall &= ~mask; in pxa_gpio_irq_type()
434 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, in pxa_gpio_irq_type()
450 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler()
451 gedr = gedr & c->irq_mask; in pxa_gpio_demux_handler()
452 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler()
457 generic_handle_domain_irq(pchip->irqdomain, in pxa_gpio_demux_handler()
471 if (in_irq == pchip->irq0) { in pxa_gpio_direct_handler()
472 generic_handle_domain_irq(pchip->irqdomain, 0); in pxa_gpio_direct_handler()
473 } else if (in_irq == pchip->irq1) { in pxa_gpio_direct_handler()
474 generic_handle_domain_irq(pchip->irqdomain, 1); in pxa_gpio_direct_handler()
486 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); in pxa_ack_muxed_gpio()
495 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); in pxa_mask_muxed_gpio()
496 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); in pxa_mask_muxed_gpio()
499 b->irq_mask &= ~GPIO_bit(gpio); in pxa_mask_muxed_gpio()
512 if (pchip->set_wake) in pxa_gpio_set_wake()
513 return pchip->set_wake(gpio, on); in pxa_gpio_set_wake()
522 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); in pxa_unmask_muxed_gpio()
524 c->irq_mask |= GPIO_bit(gpio); in pxa_unmask_muxed_gpio()
540 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; in pxa_gpio_nums()
543 switch (pxa_id->type) { in pxa_gpio_nums()
552 gpio_type = pxa_id->type; in pxa_gpio_nums()
553 count = pxa_id->gpio_nums - 1; in pxa_gpio_nums()
556 count = -EINVAL; in pxa_gpio_nums()
567 irq_set_chip_data(irq, d->host_data); in pxa_irq_domain_map()
579 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
580 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
581 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
582 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
583 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
584 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
585 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
586 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
596 gpio_id = of_device_get_match_data(&pdev->dev); in pxa_gpio_probe_dt()
597 gpio_type = gpio_id->type; in pxa_gpio_probe_dt()
599 nr_gpios = gpio_id->gpio_nums; in pxa_gpio_probe_dt()
600 pxa_last_gpio = nr_gpios - 1; in pxa_gpio_probe_dt()
602 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0); in pxa_gpio_probe_dt()
604 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); in pxa_gpio_probe_dt()
610 #define pxa_gpio_probe_dt(pdev, pchip) (-1)
623 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); in pxa_gpio_probe()
625 return -ENOMEM; in pxa_gpio_probe()
626 pchip->dev = &pdev->dev; in pxa_gpio_probe()
628 info = dev_get_platdata(&pdev->dev); in pxa_gpio_probe()
630 irq_base = info->irq_base; in pxa_gpio_probe()
632 return -EINVAL; in pxa_gpio_probe()
634 pchip->set_wake = info->gpio_set_wake; in pxa_gpio_probe()
638 return -EINVAL; in pxa_gpio_probe()
642 return -EINVAL; in pxa_gpio_probe()
644 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node, in pxa_gpio_probe()
647 if (!pchip->irqdomain) in pxa_gpio_probe()
648 return -ENOMEM; in pxa_gpio_probe()
655 return -EINVAL; in pxa_gpio_probe()
657 pchip->irq0 = irq0; in pxa_gpio_probe()
658 pchip->irq1 = irq1; in pxa_gpio_probe()
664 clk = devm_clk_get_enabled(&pdev->dev, NULL); in pxa_gpio_probe()
666 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", in pxa_gpio_probe()
678 writel_relaxed(0, c->regbase + GFER_OFFSET); in pxa_gpio_probe()
679 writel_relaxed(0, c->regbase + GRER_OFFSET); in pxa_gpio_probe()
680 writel_relaxed(~0, c->regbase + GEDR_OFFSET); in pxa_gpio_probe()
683 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); in pxa_gpio_probe()
687 ret = devm_request_irq(&pdev->dev, in pxa_gpio_probe()
689 "gpio-0", pchip); in pxa_gpio_probe()
691 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", in pxa_gpio_probe()
695 ret = devm_request_irq(&pdev->dev, in pxa_gpio_probe()
697 "gpio-1", pchip); in pxa_gpio_probe()
699 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", in pxa_gpio_probe()
702 ret = devm_request_irq(&pdev->dev, in pxa_gpio_probe()
704 "gpio-mux", pchip); in pxa_gpio_probe()
706 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", in pxa_gpio_probe()
715 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
716 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
717 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
718 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
719 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
720 { "mmp-gpio", (unsigned long)&mmp_id },
721 { "mmp2-gpio", (unsigned long)&mmp2_id },
722 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
729 .name = "pxa-gpio",
764 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); in pxa_gpio_suspend()
765 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_suspend()
766 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); in pxa_gpio_suspend()
767 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); in pxa_gpio_suspend()
770 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); in pxa_gpio_suspend()
786 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); in pxa_gpio_resume()
787 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); in pxa_gpio_resume()
789 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); in pxa_gpio_resume()
790 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); in pxa_gpio_resume()
791 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); in pxa_gpio_resume()