1 // SPDX-License-Identifier: GPL-2.0-only
51 	raw_spinlock_t		lock;  member
62 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)  in pl061_get_direction()  argument
66 	if (readb(pl061->base + GPIODIR) & BIT(offset))  in pl061_get_direction()
72 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)  in pl061_direction_input()  argument
78 	raw_spin_lock_irqsave(&pl061->lock, flags);  in pl061_direction_input()
79 	gpiodir = readb(pl061->base + GPIODIR);  in pl061_direction_input()
80 	gpiodir &= ~(BIT(offset));  in pl061_direction_input()
81 	writeb(gpiodir, pl061->base + GPIODIR);  in pl061_direction_input()
82 	raw_spin_unlock_irqrestore(&pl061->lock, flags);  in pl061_direction_input()
87 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,  in pl061_direction_output()  argument
94 	raw_spin_lock_irqsave(&pl061->lock, flags);  in pl061_direction_output()
95 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));  in pl061_direction_output()
96 	gpiodir = readb(pl061->base + GPIODIR);  in pl061_direction_output()
97 	gpiodir |= BIT(offset);  in pl061_direction_output()
98 	writeb(gpiodir, pl061->base + GPIODIR);  in pl061_direction_output()
104 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));  in pl061_direction_output()
105 	raw_spin_unlock_irqrestore(&pl061->lock, flags);  in pl061_direction_output()
110 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)  in pl061_get_value()  argument
114 	return !!readb(pl061->base + (BIT(offset + 2)));  in pl061_get_value()
117 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)  in pl061_set_value()  argument
121 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));  in pl061_set_value()
128 	int offset = irqd_to_hwirq(d);  in pl061_irq_type()  local
131 	u8 bit = BIT(offset);  in pl061_irq_type()
133 	if (offset < 0 || offset >= PL061_GPIO_NR)  in pl061_irq_type()
134 		return -EINVAL;  in pl061_irq_type()
139 		dev_err(gc->parent,  in pl061_irq_type()
142 			offset);  in pl061_irq_type()
143 		return -EINVAL;  in pl061_irq_type()
147 	raw_spin_lock_irqsave(&pl061->lock, flags);  in pl061_irq_type()
149 	gpioiev = readb(pl061->base + GPIOIEV);  in pl061_irq_type()
150 	gpiois = readb(pl061->base + GPIOIS);  in pl061_irq_type()
151 	gpioibe = readb(pl061->base + GPIOIBE);  in pl061_irq_type()
166 		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",  in pl061_irq_type()
167 			offset,  in pl061_irq_type()
175 		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);  in pl061_irq_type()
190 		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",  in pl061_irq_type()
191 			offset,  in pl061_irq_type()
199 		dev_warn(gc->parent, "no trigger selected for line %d\n",  in pl061_irq_type()
200 			 offset);  in pl061_irq_type()
203 	writeb(gpiois, pl061->base + GPIOIS);  in pl061_irq_type()
204 	writeb(gpioibe, pl061->base + GPIOIBE);  in pl061_irq_type()
205 	writeb(gpioiev, pl061->base + GPIOIEV);  in pl061_irq_type()
207 	raw_spin_unlock_irqrestore(&pl061->lock, flags);  in pl061_irq_type()
215 	int offset;  in pl061_irq_handler()  local
222 	pending = readb(pl061->base + GPIOMIS);  in pl061_irq_handler()
224 		for_each_set_bit(offset, &pending, PL061_GPIO_NR)  in pl061_irq_handler()
225 			generic_handle_domain_irq(gc->irq.domain,  in pl061_irq_handler()
226 						  offset);  in pl061_irq_handler()
239 	raw_spin_lock(&pl061->lock);  in pl061_irq_mask()
240 	gpioie = readb(pl061->base + GPIOIE) & ~mask;  in pl061_irq_mask()
241 	writeb(gpioie, pl061->base + GPIOIE);  in pl061_irq_mask()
242 	raw_spin_unlock(&pl061->lock);  in pl061_irq_mask()
244 	gpiochip_disable_irq(gc, d->hwirq);  in pl061_irq_mask()
254 	gpiochip_enable_irq(gc, d->hwirq);  in pl061_irq_unmask()
256 	raw_spin_lock(&pl061->lock);  in pl061_irq_unmask()
257 	gpioie = readb(pl061->base + GPIOIE) | mask;  in pl061_irq_unmask()
258 	writeb(gpioie, pl061->base + GPIOIE);  in pl061_irq_unmask()
259 	raw_spin_unlock(&pl061->lock);  in pl061_irq_unmask()
263  * pl061_irq_ack() - ACK an edge IRQ
267  * in the GPIOIC (interrupt-clear) register. For level IRQs this is
276 	raw_spin_lock(&pl061->lock);  in pl061_irq_ack()
277 	writeb(mask, pl061->base + GPIOIC);  in pl061_irq_ack()
278 	raw_spin_unlock(&pl061->lock);  in pl061_irq_ack()
286 	return irq_set_irq_wake(pl061->parent_irq, state);  in pl061_irq_set_wake()
293 	seq_printf(p, dev_name(gc->parent));  in pl061_irq_print_chip()
309 	struct device *dev = &adev->dev;  in pl061_probe()
316 		return -ENOMEM;  in pl061_probe()
318 	pl061->base = devm_ioremap_resource(dev, &adev->res);  in pl061_probe()
319 	if (IS_ERR(pl061->base))  in pl061_probe()
320 		return PTR_ERR(pl061->base);  in pl061_probe()
322 	raw_spin_lock_init(&pl061->lock);  in pl061_probe()
323 	pl061->gc.request = gpiochip_generic_request;  in pl061_probe()
324 	pl061->gc.free = gpiochip_generic_free;  in pl061_probe()
325 	pl061->gc.base = -1;  in pl061_probe()
326 	pl061->gc.get_direction = pl061_get_direction;  in pl061_probe()
327 	pl061->gc.direction_input = pl061_direction_input;  in pl061_probe()
328 	pl061->gc.direction_output = pl061_direction_output;  in pl061_probe()
329 	pl061->gc.get = pl061_get_value;  in pl061_probe()
330 	pl061->gc.set = pl061_set_value;  in pl061_probe()
331 	pl061->gc.ngpio = PL061_GPIO_NR;  in pl061_probe()
332 	pl061->gc.label = dev_name(dev);  in pl061_probe()
333 	pl061->gc.parent = dev;  in pl061_probe()
334 	pl061->gc.owner = THIS_MODULE;  in pl061_probe()
339 	writeb(0, pl061->base + GPIOIE); /* disable irqs */  in pl061_probe()
340 	irq = adev->irq[0];  in pl061_probe()
342 		dev_warn(&adev->dev, "IRQ support disabled\n");  in pl061_probe()
343 	pl061->parent_irq = irq;  in pl061_probe()
345 	girq = &pl061->gc.irq;  in pl061_probe()
347 	girq->parent_handler = pl061_irq_handler;  in pl061_probe()
348 	girq->num_parents = 1;  in pl061_probe()
349 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in pl061_probe()
351 	if (!girq->parents)  in pl061_probe()
352 		return -ENOMEM;  in pl061_probe()
353 	girq->parents[0] = irq;  in pl061_probe()
354 	girq->default_type = IRQ_TYPE_NONE;  in pl061_probe()
355 	girq->handler = handle_bad_irq;  in pl061_probe()
357 	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);  in pl061_probe()
371 	int offset;  in pl061_suspend()  local
373 	pl061->csave_regs.gpio_data = 0;  in pl061_suspend()
374 	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);  in pl061_suspend()
375 	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);  in pl061_suspend()
376 	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);  in pl061_suspend()
377 	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);  in pl061_suspend()
378 	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);  in pl061_suspend()
380 	for (offset = 0; offset < PL061_GPIO_NR; offset++) {  in pl061_suspend()
381 		if (pl061->csave_regs.gpio_dir & (BIT(offset)))  in pl061_suspend()
382 			pl061->csave_regs.gpio_data |=  in pl061_suspend()
383 				pl061_get_value(&pl061->gc, offset) << offset;  in pl061_suspend()
392 	int offset;  in pl061_resume()  local
394 	for (offset = 0; offset < PL061_GPIO_NR; offset++) {  in pl061_resume()
395 		if (pl061->csave_regs.gpio_dir & (BIT(offset)))  in pl061_resume()
396 			pl061_direction_output(&pl061->gc, offset,  in pl061_resume()
397 					pl061->csave_regs.gpio_data &  in pl061_resume()
398 					(BIT(offset)));  in pl061_resume()
400 			pl061_direction_input(&pl061->gc, offset);  in pl061_resume()
403 	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);  in pl061_resume()
404 	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);  in pl061_resume()
405 	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);  in pl061_resume()
406 	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);  in pl061_resume()