Lines Matching +full:pm +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0
32 u32 pm; member
47 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
48 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
59 * struct pch_gpio_reg_data - The register store data.
63 * @pm_reg: To store contents of PM register.
67 * (Only ML7223 Bus-n)
80 * struct pch_gpio - GPIO private data structure.
109 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_set()
110 reg_val = ioread32(&chip->reg->po); in pch_gpio_set()
116 iowrite32(reg_val, &chip->reg->po); in pch_gpio_set()
117 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_set()
124 return !!(ioread32(&chip->reg->pi) & BIT(nr)); in pch_gpio_get()
131 u32 pm; in pch_gpio_direction_output() local
135 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_direction_output()
137 reg_val = ioread32(&chip->reg->po); in pch_gpio_direction_output()
142 iowrite32(reg_val, &chip->reg->po); in pch_gpio_direction_output()
144 pm = ioread32(&chip->reg->pm); in pch_gpio_direction_output()
145 pm &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_direction_output()
146 pm |= BIT(nr); in pch_gpio_direction_output()
147 iowrite32(pm, &chip->reg->pm); in pch_gpio_direction_output()
149 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_direction_output()
157 u32 pm; in pch_gpio_direction_input() local
160 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_direction_input()
161 pm = ioread32(&chip->reg->pm); in pch_gpio_direction_input()
162 pm &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_direction_input()
163 pm &= ~BIT(nr); in pch_gpio_direction_input()
164 iowrite32(pm, &chip->reg->pm); in pch_gpio_direction_input()
165 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_direction_input()
175 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); in pch_gpio_save_reg_conf()
176 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); in pch_gpio_save_reg_conf()
177 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); in pch_gpio_save_reg_conf()
178 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); in pch_gpio_save_reg_conf()
179 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); in pch_gpio_save_reg_conf()
180 if (chip->ioh == INTEL_EG20T_PCH) in pch_gpio_save_reg_conf()
181 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); in pch_gpio_save_reg_conf()
182 if (chip->ioh == OKISEMI_ML7223n_IOH) in pch_gpio_save_reg_conf()
183 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel); in pch_gpio_save_reg_conf()
191 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); in pch_gpio_restore_reg_conf()
192 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); in pch_gpio_restore_reg_conf()
194 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); in pch_gpio_restore_reg_conf()
195 /* to store contents of PM register */ in pch_gpio_restore_reg_conf()
196 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); in pch_gpio_restore_reg_conf()
197 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); in pch_gpio_restore_reg_conf()
198 if (chip->ioh == INTEL_EG20T_PCH) in pch_gpio_restore_reg_conf()
199 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); in pch_gpio_restore_reg_conf()
200 if (chip->ioh == OKISEMI_ML7223n_IOH) in pch_gpio_restore_reg_conf()
201 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); in pch_gpio_restore_reg_conf()
208 return chip->irq_base + offset; in pch_gpio_to_irq()
213 struct gpio_chip *gpio = &chip->gpio; in pch_gpio_setup()
215 gpio->label = dev_name(chip->dev); in pch_gpio_setup()
216 gpio->parent = chip->dev; in pch_gpio_setup()
217 gpio->owner = THIS_MODULE; in pch_gpio_setup()
218 gpio->direction_input = pch_gpio_direction_input; in pch_gpio_setup()
219 gpio->get = pch_gpio_get; in pch_gpio_setup()
220 gpio->direction_output = pch_gpio_direction_output; in pch_gpio_setup()
221 gpio->set = pch_gpio_set; in pch_gpio_setup()
222 gpio->base = -1; in pch_gpio_setup()
223 gpio->ngpio = gpio_pins[chip->ioh]; in pch_gpio_setup()
224 gpio->can_sleep = false; in pch_gpio_setup()
225 gpio->to_irq = pch_gpio_to_irq; in pch_gpio_setup()
231 struct pch_gpio *chip = gc->private; in pch_irq_type()
235 int ch, irq = d->irq; in pch_irq_type()
237 ch = irq - chip->irq_base; in pch_irq_type()
238 if (irq < chip->irq_base + 8) { in pch_irq_type()
239 im_reg = &chip->reg->im0; in pch_irq_type()
240 im_pos = ch - 0; in pch_irq_type()
242 im_reg = &chip->reg->im1; in pch_irq_type()
243 im_pos = ch - 8; in pch_irq_type()
245 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos); in pch_irq_type()
267 spin_lock_irqsave(&chip->spinlock, flags); in pch_irq_type()
279 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_irq_type()
286 struct pch_gpio *chip = gc->private; in pch_irq_unmask()
288 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr); in pch_irq_unmask()
294 struct pch_gpio *chip = gc->private; in pch_irq_mask()
296 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask); in pch_irq_mask()
302 struct pch_gpio *chip = gc->private; in pch_irq_ack()
304 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr); in pch_irq_ack()
310 unsigned long reg_val = ioread32(&chip->reg->istatus); in pch_gpio_handler()
313 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val); in pch_gpio_handler()
315 reg_val &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_handler()
317 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) in pch_gpio_handler()
318 generic_handle_irq(chip->irq_base + i); in pch_gpio_handler()
331 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start, in pch_gpio_alloc_generic_chip()
332 chip->base, handle_simple_irq); in pch_gpio_alloc_generic_chip()
334 return -ENOMEM; in pch_gpio_alloc_generic_chip()
336 gc->private = chip; in pch_gpio_alloc_generic_chip()
337 ct = gc->chip_types; in pch_gpio_alloc_generic_chip()
339 ct->chip.irq_ack = pch_irq_ack; in pch_gpio_alloc_generic_chip()
340 ct->chip.irq_mask = pch_irq_mask; in pch_gpio_alloc_generic_chip()
341 ct->chip.irq_unmask = pch_irq_unmask; in pch_gpio_alloc_generic_chip()
342 ct->chip.irq_set_type = pch_irq_type; in pch_gpio_alloc_generic_chip()
344 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), in pch_gpio_alloc_generic_chip()
354 struct device *dev = &pdev->dev; in pch_gpio_probe()
361 return -ENOMEM; in pch_gpio_probe()
363 chip->dev = dev; in pch_gpio_probe()
372 chip->base = pcim_iomap_table(pdev)[1]; in pch_gpio_probe()
373 chip->ioh = id->driver_data; in pch_gpio_probe()
374 chip->reg = chip->base; in pch_gpio_probe()
376 spin_lock_init(&chip->spinlock); in pch_gpio_probe()
379 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip); in pch_gpio_probe()
383 irq_base = devm_irq_alloc_descs(dev, -1, 0, in pch_gpio_probe()
384 gpio_pins[chip->ioh], NUMA_NO_NODE); in pch_gpio_probe()
387 chip->irq_base = -1; in pch_gpio_probe()
390 chip->irq_base = irq_base; in pch_gpio_probe()
393 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask); in pch_gpio_probe()
394 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien); in pch_gpio_probe()
396 ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler, in pch_gpio_probe()
401 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); in pch_gpio_probe()
409 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_suspend()
411 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_suspend()
421 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_resume()
422 iowrite32(0x01, &chip->reg->reset); in pch_gpio_resume()
423 iowrite32(0x00, &chip->reg->reset); in pch_gpio_resume()
425 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_resume()
446 .pm = &pch_gpio_pm_ops,