Lines Matching +full:davinci +full:- +full:gpio +full:- +full:unbanked
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DaVinci GPIO Support
5 * Copyright (c) 2006-2007 David Brownell
9 #include <linux/gpio/driver.h>
22 #include <linux/platform_data/gpio-davinci.h>
27 #include <asm-generic/gpio.h>
47 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
61 /* Serialize access to GPIO registers */
70 static inline u32 __gpio_mask(unsigned gpio) in __gpio_mask() argument
72 return 1 << (gpio % 32); in __gpio_mask()
86 /*--------------------------------------------------------------------------*/
88 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
99 g = d->regs[bank]; in __davinci_direction()
100 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
101 temp = readl_relaxed(&g->dir); in __davinci_direction()
104 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
108 writel_relaxed(temp, &g->dir); in __davinci_direction()
109 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
129 * Note that changes are synched to the GPIO clock, so reading values back
138 g = d->regs[bank]; in davinci_gpio_get()
140 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
144 * Assuming the pin is muxed as a gpio output, set its output value.
153 g = d->regs[bank]; in davinci_gpio_set()
156 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
162 struct device_node *dn = pdev->dev.of_node; in davinci_gpio_get_pdata()
167 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) in davinci_gpio_get_pdata()
168 return dev_get_platdata(&pdev->dev); in davinci_gpio_get_pdata()
170 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in davinci_gpio_get_pdata()
178 pdata->ngpio = val; in davinci_gpio_get_pdata()
180 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); in davinci_gpio_get_pdata()
184 pdata->gpio_unbanked = val; in davinci_gpio_get_pdata()
189 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); in davinci_gpio_get_pdata()
199 struct device *dev = &pdev->dev; in davinci_gpio_probe()
204 return -EINVAL; in davinci_gpio_probe()
207 dev->platform_data = pdata; in davinci_gpio_probe()
210 * The gpio banks conceptually expose a segmented bitmap, in davinci_gpio_probe()
211 * and "ngpio" is one more than the largest zero-based in davinci_gpio_probe()
214 ngpio = pdata->ngpio; in davinci_gpio_probe()
217 return -EINVAL; in davinci_gpio_probe()
224 * If there are unbanked interrupts then the number of in davinci_gpio_probe()
228 if (pdata->gpio_unbanked) in davinci_gpio_probe()
229 nirq = pdata->gpio_unbanked; in davinci_gpio_probe()
235 return -ENOMEM; in davinci_gpio_probe()
242 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
243 if (chips->irqs[i] < 0) in davinci_gpio_probe()
244 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); in davinci_gpio_probe()
247 chips->chip.label = dev_name(dev); in davinci_gpio_probe()
249 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
250 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
251 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
252 chips->chip.set = davinci_gpio_set; in davinci_gpio_probe()
254 chips->chip.ngpio = ngpio; in davinci_gpio_probe()
255 chips->chip.base = pdata->no_auto_base ? pdata->base : -1; in davinci_gpio_probe()
258 chips->chip.of_gpio_n_cells = 2; in davinci_gpio_probe()
259 chips->chip.parent = dev; in davinci_gpio_probe()
260 chips->chip.request = gpiochip_generic_request; in davinci_gpio_probe()
261 chips->chip.free = gpiochip_generic_free; in davinci_gpio_probe()
263 spin_lock_init(&chips->lock); in davinci_gpio_probe()
267 chips->regs[bank] = gpio_base + offset_array[bank]; in davinci_gpio_probe()
269 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); in davinci_gpio_probe()
281 /*--------------------------------------------------------------------------*/
298 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
299 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
313 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
315 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
321 return -EINVAL; in gpio_irq_type()
327 .name = "GPIO",
343 bank_num = irqdata->bank_num; in gpio_irq_handler()
344 g = irqdata->regs; in gpio_irq_handler()
345 d = irqdata->chip; in gpio_irq_handler()
359 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
362 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
374 generic_handle_domain_irq(d->irq_domain, hw_irq); in gpio_irq_handler()
378 /* now it may re-trigger */ in gpio_irq_handler()
385 if (d->irq_domain) in gpio_to_irq_banked()
386 return irq_create_mapping(d->irq_domain, offset); in gpio_to_irq_banked()
388 return -ENXIO; in gpio_to_irq_banked()
397 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
399 if (offset < d->gpio_unbanked) in gpio_to_irq_unbanked()
400 return d->irqs[offset]; in gpio_to_irq_unbanked()
402 return -ENODEV; in gpio_to_irq_unbanked()
412 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
414 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
418 return -EINVAL; in gpio_irq_type_unbanked()
423 return -EINVAL; in gpio_irq_type_unbanked()
426 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
428 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
438 (struct davinci_gpio_controller *)d->host_data; in davinci_gpio_irq_map()
439 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map()
484 unsigned gpio, bank; in davinci_gpio_irq_setup() local
490 struct device *dev = &pdev->dev; in davinci_gpio_irq_setup()
492 struct davinci_gpio_platform_data *pdata = dev->platform_data; in davinci_gpio_irq_setup()
507 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; in davinci_gpio_irq_setup()
509 ngpio = pdata->ngpio; in davinci_gpio_irq_setup()
511 clk = devm_clk_get(dev, "gpio"); in davinci_gpio_irq_setup()
513 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); in davinci_gpio_irq_setup()
521 if (!pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
522 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); in davinci_gpio_irq_setup()
529 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, in davinci_gpio_irq_setup()
535 return -ENODEV; in davinci_gpio_irq_setup()
541 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
545 chips->chip.to_irq = gpio_to_irq_banked; in davinci_gpio_irq_setup()
546 chips->irq_domain = irq_domain; in davinci_gpio_irq_setup()
549 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO in davinci_gpio_irq_setup()
553 if (pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
554 /* pass "bank 0" GPIO IRQs to AINTC */ in davinci_gpio_irq_setup()
555 chips->chip.to_irq = gpio_to_irq_unbanked; in davinci_gpio_irq_setup()
556 chips->gpio_unbanked = pdata->gpio_unbanked; in davinci_gpio_irq_setup()
557 binten = GENMASK(pdata->gpio_unbanked / 16, 0); in davinci_gpio_irq_setup()
559 /* AINTC handles mask/unmask; GPIO handles triggering */ in davinci_gpio_irq_setup()
560 irq = chips->irqs[0]; in davinci_gpio_irq_setup()
562 irq_chip->name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
563 irq_chip->irq_set_type = gpio_irq_type_unbanked; in davinci_gpio_irq_setup()
566 g = chips->regs[0]; in davinci_gpio_irq_setup()
567 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
568 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
571 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { in davinci_gpio_irq_setup()
572 irq_set_chip(chips->irqs[gpio], irq_chip); in davinci_gpio_irq_setup()
573 irq_set_handler_data(chips->irqs[gpio], chips); in davinci_gpio_irq_setup()
574 irq_set_status_flags(chips->irqs[gpio], in davinci_gpio_irq_setup()
582 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we in davinci_gpio_irq_setup()
585 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { in davinci_gpio_irq_setup()
590 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
591 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
592 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
596 * gpio irqs. Pass the irq bank's corresponding controller to in davinci_gpio_irq_setup()
599 irqdata = devm_kzalloc(&pdev->dev, in davinci_gpio_irq_setup()
605 return -ENOMEM; in davinci_gpio_irq_setup()
608 irqdata->regs = g; in davinci_gpio_irq_setup()
609 irqdata->bank_num = bank; in davinci_gpio_irq_setup()
610 irqdata->chip = chips; in davinci_gpio_irq_setup()
612 irq_set_chained_handler_and_data(chips->irqs[bank], in davinci_gpio_irq_setup()
620 * BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
636 base = chips->regs[0] - offset_array[0]; in davinci_gpio_save_context()
637 chips->binten_context = readl_relaxed(base + BINTEN); in davinci_gpio_save_context()
640 g = chips->regs[bank]; in davinci_gpio_save_context()
641 context = &chips->context[bank]; in davinci_gpio_save_context()
642 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
643 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
644 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
645 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
652 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
663 base = chips->regs[0] - offset_array[0]; in davinci_gpio_restore_context()
665 if (readl_relaxed(base + BINTEN) != chips->binten_context) in davinci_gpio_restore_context()
666 writel_relaxed(chips->binten_context, base + BINTEN); in davinci_gpio_restore_context()
669 g = chips->regs[bank]; in davinci_gpio_restore_context()
670 context = &chips->context[bank]; in davinci_gpio_restore_context()
671 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
672 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
673 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
674 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
675 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
676 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
677 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
678 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()
686 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); in davinci_gpio_suspend()
697 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); in davinci_gpio_resume()
708 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
709 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
710 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
725 * GPIO driver registration needs to be done before machine_init functions
726 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.