43 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)  in ath79_gpio_read()  argument
45 	return readl(ctrl->base + reg);  in ath79_gpio_read()
48 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,  in ath79_gpio_write()  argument
51 	writel(val, ctrl->base + reg);  in ath79_gpio_write()
55 	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)  in ath79_gpio_update_bits()  argument
59 	old_val = ath79_gpio_read(ctrl, reg);  in ath79_gpio_update_bits()
63 		ath79_gpio_write(ctrl, reg, new_val);  in ath79_gpio_update_bits()
70 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_unmask()  local
74 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_unmask()
75 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);  in ath79_gpio_irq_unmask()
76 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_unmask()
81 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_mask()  local
85 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_mask()
86 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);  in ath79_gpio_irq_mask()
87 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_mask()
92 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_enable()  local
96 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_enable()
97 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);  in ath79_gpio_irq_enable()
98 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);  in ath79_gpio_irq_enable()
99 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_enable()
104 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_disable()  local
108 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_disable()
109 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);  in ath79_gpio_irq_disable()
110 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);  in ath79_gpio_irq_disable()
111 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_disable()
117 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);  in ath79_gpio_irq_set_type()  local
142 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_set_type()
145 		ctrl->both_edges |= mask;  in ath79_gpio_irq_set_type()
146 		polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);  in ath79_gpio_irq_set_type()
148 		ctrl->both_edges &= ~mask;  in ath79_gpio_irq_set_type()
156 		ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);  in ath79_gpio_irq_set_type()
159 		ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);  in ath79_gpio_irq_set_type()
161 		ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);  in ath79_gpio_irq_set_type()
165 			ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);  in ath79_gpio_irq_set_type()
167 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_set_type()
185 	struct ath79_gpio_ctrl *ctrl =  in ath79_gpio_irq_handler()  local
193 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in ath79_gpio_irq_handler()
195 	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);  in ath79_gpio_irq_handler()
198 	both_edges = ctrl->both_edges & pending;  in ath79_gpio_irq_handler()
200 		state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);  in ath79_gpio_irq_handler()
201 		ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,  in ath79_gpio_irq_handler()
205 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in ath79_gpio_irq_handler()
225 	struct ath79_gpio_ctrl *ctrl;  in ath79_gpio_probe()  local
231 	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);  in ath79_gpio_probe()
232 	if (!ctrl)  in ath79_gpio_probe()
255 	ctrl->base = devm_platform_ioremap_resource(pdev, 0);  in ath79_gpio_probe()
256 	if (IS_ERR(ctrl->base))  in ath79_gpio_probe()
257 		return PTR_ERR(ctrl->base);  in ath79_gpio_probe()
259 	raw_spin_lock_init(&ctrl->lock);  in ath79_gpio_probe()
260 	err = bgpio_init(&ctrl->gc, dev, 4,  in ath79_gpio_probe()
261 			ctrl->base + AR71XX_GPIO_REG_IN,  in ath79_gpio_probe()
262 			ctrl->base + AR71XX_GPIO_REG_SET,  in ath79_gpio_probe()
263 			ctrl->base + AR71XX_GPIO_REG_CLEAR,  in ath79_gpio_probe()
264 			oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,  in ath79_gpio_probe()
265 			oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,  in ath79_gpio_probe()
272 	ctrl->gc.base = 0;  in ath79_gpio_probe()
276 		girq = &ctrl->gc.irq;  in ath79_gpio_probe()
289 	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);  in ath79_gpio_probe()