1 // SPDX-License-Identifier: GPL-2.0-or-later
34 	raw_spinlock_t lock;  member
109 		return gpio->base + bank->val_regs + GPIO_VAL_VALUE;  in bank_reg()
111 		return gpio->base + bank->rdata_reg;  in bank_reg()
113 		return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;  in bank_reg()
115 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;  in bank_reg()
117 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;  in bank_reg()
119 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;  in bank_reg()
121 		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;  in bank_reg()
123 		return gpio->base + bank->tolerance_regs;  in bank_reg()
134 static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)  in to_bank()  argument
138 	bank = GPIO_BANK(offset);  in to_bank()
163 static bool aspeed_sgpio_is_input(unsigned int offset)  in aspeed_sgpio_is_input()  argument
165 	return !(offset % 2);  in aspeed_sgpio_is_input()
168 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)  in aspeed_sgpio_get()  argument
171 	const struct aspeed_sgpio_bank *bank = to_bank(offset);  in aspeed_sgpio_get()
176 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_get()
178 	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;  in aspeed_sgpio_get()
179 	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));  in aspeed_sgpio_get()
181 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_get()
186 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)  in sgpio_set_value()  argument
189 	const struct aspeed_sgpio_bank *bank = to_bank(offset);  in sgpio_set_value()
193 	if (aspeed_sgpio_is_input(offset))  in sgpio_set_value()
194 		return -EINVAL;  in sgpio_set_value()
204 		reg |= GPIO_BIT(offset);  in sgpio_set_value()
206 		reg &= ~GPIO_BIT(offset);  in sgpio_set_value()
213 static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)  in aspeed_sgpio_set()  argument
218 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_set()
220 	sgpio_set_value(gc, offset, val);  in aspeed_sgpio_set()
222 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_set()
225 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)  in aspeed_sgpio_dir_in()  argument
227 	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;  in aspeed_sgpio_dir_in()
230 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)  in aspeed_sgpio_dir_out()  argument
237 	 * error-out in sgpio_set_value if this isn't an output GPIO */  in aspeed_sgpio_dir_out()
239 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_dir_out()
240 	rc = sgpio_set_value(gc, offset, val);  in aspeed_sgpio_dir_out()
241 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_dir_out()
246 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)  in aspeed_sgpio_get_direction()  argument
248 	return !!aspeed_sgpio_is_input(offset);  in aspeed_sgpio_get_direction()
254 					u32 *bit, int *offset)  in irqd_to_aspeed_sgpio_data()  argument
258 	*offset = irqd_to_hwirq(d);  in irqd_to_aspeed_sgpio_data()
263 	*bank = to_bank(*offset);  in irqd_to_aspeed_sgpio_data()
264 	*bit = GPIO_BIT(*offset);  in irqd_to_aspeed_sgpio_data()
273 	int offset;  in aspeed_sgpio_irq_ack()  local
276 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);  in aspeed_sgpio_irq_ack()
280 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_irq_ack()
284 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_irq_ack()
294 	int offset;  in aspeed_sgpio_irq_set_mask()  local
296 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);  in aspeed_sgpio_irq_set_mask()
299 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_irq_set_mask()
309 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_irq_set_mask()
333 	int offset;  in aspeed_sgpio_set_type()  local
335 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);  in aspeed_sgpio_set_type()
355 		return -EINVAL;  in aspeed_sgpio_set_type()
358 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_set_type()
375 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_set_type()
398 			generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);  in aspeed_sgpio_irq_handler()
415 	gpio->irq = rc;  in aspeed_sgpio_setup_irqs()
426 	gpio->intc.name = dev_name(&pdev->dev);  in aspeed_sgpio_setup_irqs()
427 	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;  in aspeed_sgpio_setup_irqs()
428 	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;  in aspeed_sgpio_setup_irqs()
429 	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;  in aspeed_sgpio_setup_irqs()
430 	gpio->intc.irq_set_type = aspeed_sgpio_set_type;  in aspeed_sgpio_setup_irqs()
432 	irq = &gpio->chip.irq;  in aspeed_sgpio_setup_irqs()
433 	irq->chip = &gpio->intc;  in aspeed_sgpio_setup_irqs()
434 	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;  in aspeed_sgpio_setup_irqs()
435 	irq->handler = handle_bad_irq;  in aspeed_sgpio_setup_irqs()
436 	irq->default_type = IRQ_TYPE_NONE;  in aspeed_sgpio_setup_irqs()
437 	irq->parent_handler = aspeed_sgpio_irq_handler;  in aspeed_sgpio_setup_irqs()
438 	irq->parent_handler_data = gpio;  in aspeed_sgpio_setup_irqs()
439 	irq->parents = &gpio->irq;  in aspeed_sgpio_setup_irqs()
440 	irq->num_parents = 1;  in aspeed_sgpio_setup_irqs()
445 		/* set falling or level-low irq */  in aspeed_sgpio_setup_irqs()
461 					unsigned int offset, bool enable)  in aspeed_sgpio_reset_tolerance()  argument
468 	reg = bank_reg(gpio, to_bank(offset), reg_tolerance);  in aspeed_sgpio_reset_tolerance()
470 	raw_spin_lock_irqsave(&gpio->lock, flags);  in aspeed_sgpio_reset_tolerance()
475 		val |= GPIO_BIT(offset);  in aspeed_sgpio_reset_tolerance()
477 		val &= ~GPIO_BIT(offset);  in aspeed_sgpio_reset_tolerance()
481 	raw_spin_unlock_irqrestore(&gpio->lock, flags);  in aspeed_sgpio_reset_tolerance()
486 static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,  in aspeed_sgpio_set_config()  argument
493 		return aspeed_sgpio_reset_tolerance(chip, offset, arg);  in aspeed_sgpio_set_config()
495 	return -ENOTSUPP;  in aspeed_sgpio_set_config()
503 	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
504 	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
505 	{ .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
519 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);  in aspeed_sgpio_probe()
521 		return -ENOMEM;  in aspeed_sgpio_probe()
523 	gpio->base = devm_platform_ioremap_resource(pdev, 0);  in aspeed_sgpio_probe()
524 	if (IS_ERR(gpio->base))  in aspeed_sgpio_probe()
525 		return PTR_ERR(gpio->base);  in aspeed_sgpio_probe()
527 	pdata = device_get_match_data(&pdev->dev);  in aspeed_sgpio_probe()
529 		return -EINVAL;  in aspeed_sgpio_probe()
531 	pin_mask = pdata->pin_mask;  in aspeed_sgpio_probe()
533 	rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);  in aspeed_sgpio_probe()
535 		dev_err(&pdev->dev, "Could not read ngpios property\n");  in aspeed_sgpio_probe()
536 		return -EINVAL;  in aspeed_sgpio_probe()
538 		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",  in aspeed_sgpio_probe()
540 		return -EINVAL;  in aspeed_sgpio_probe()
543 	rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);  in aspeed_sgpio_probe()
545 		dev_err(&pdev->dev, "Could not read bus-frequency property\n");  in aspeed_sgpio_probe()
546 		return -EINVAL;  in aspeed_sgpio_probe()
549 	gpio->pclk = devm_clk_get(&pdev->dev, NULL);  in aspeed_sgpio_probe()
550 	if (IS_ERR(gpio->pclk)) {  in aspeed_sgpio_probe()
551 		dev_err(&pdev->dev, "devm_clk_get failed\n");  in aspeed_sgpio_probe()
552 		return PTR_ERR(gpio->pclk);  in aspeed_sgpio_probe()
555 	apb_freq = clk_get_rate(gpio->pclk);  in aspeed_sgpio_probe()
564 	 *	GPIO254[31:16] = PCLK / (frequency * 2) - 1  in aspeed_sgpio_probe()
567 		return -EINVAL;  in aspeed_sgpio_probe()
569 	sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;  in aspeed_sgpio_probe()
571 	if (sgpio_clk_div > (1 << 16) - 1)  in aspeed_sgpio_probe()
572 		return -EINVAL;  in aspeed_sgpio_probe()
576 		  ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);  in aspeed_sgpio_probe()
578 	raw_spin_lock_init(&gpio->lock);  in aspeed_sgpio_probe()
580 	gpio->chip.parent = &pdev->dev;  in aspeed_sgpio_probe()
581 	gpio->chip.ngpio = nr_gpios * 2;  in aspeed_sgpio_probe()
582 	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;  in aspeed_sgpio_probe()
583 	gpio->chip.direction_input = aspeed_sgpio_dir_in;  in aspeed_sgpio_probe()
584 	gpio->chip.direction_output = aspeed_sgpio_dir_out;  in aspeed_sgpio_probe()
585 	gpio->chip.get_direction = aspeed_sgpio_get_direction;  in aspeed_sgpio_probe()
586 	gpio->chip.request = NULL;  in aspeed_sgpio_probe()
587 	gpio->chip.free = NULL;  in aspeed_sgpio_probe()
588 	gpio->chip.get = aspeed_sgpio_get;  in aspeed_sgpio_probe()
589 	gpio->chip.set = aspeed_sgpio_set;  in aspeed_sgpio_probe()
590 	gpio->chip.set_config = aspeed_sgpio_set_config;  in aspeed_sgpio_probe()
591 	gpio->chip.label = dev_name(&pdev->dev);  in aspeed_sgpio_probe()
592 	gpio->chip.base = -1;  in aspeed_sgpio_probe()
596 	rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);  in aspeed_sgpio_probe()