Lines Matching refs:GENMASK_ULL
71 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
74 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
77 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
83 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
97 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
103 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
104 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
105 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
106 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
110 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
112 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
124 #define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
140 #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
141 #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
142 #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
153 #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
164 #define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
170 #define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
171 #define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */