Lines Matching +full:0 +full:xc400
16 #define TI_SCI_MSG_ENABLE_WDT 0x0000
17 #define TI_SCI_MSG_WAKE_RESET 0x0001
18 #define TI_SCI_MSG_VERSION 0x0002
19 #define TI_SCI_MSG_WAKE_REASON 0x0003
20 #define TI_SCI_MSG_GOODBYE 0x0004
21 #define TI_SCI_MSG_SYS_RESET 0x0005
24 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
25 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
26 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
29 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
30 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
31 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
32 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
33 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
34 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
35 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
36 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
39 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
42 #define TI_SCI_MSG_SET_IRQ 0x1000
43 #define TI_SCI_MSG_FREE_IRQ 0x1001
47 #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100
48 #define TI_SCI_MSG_RM_RING_FREE 0x1101
49 #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
50 #define TI_SCI_MSG_RM_RING_RESET 0x1103
51 #define TI_SCI_MSG_RM_RING_CFG 0x1110
54 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
55 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
57 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
58 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
59 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
60 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
61 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
62 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
64 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
65 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
66 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
67 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
68 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
69 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
70 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
71 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
74 #define TI_SCI_MSG_PROC_REQUEST 0xc000
75 #define TI_SCI_MSG_PROC_RELEASE 0xc001
76 #define TI_SCI_MSG_PROC_HANDOVER 0xc005
77 #define TI_SCI_MSG_SET_CONFIG 0xc100
78 #define TI_SCI_MSG_SET_CTRL 0xc101
79 #define TI_SCI_MSG_GET_STATUS 0xc400
93 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
94 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
96 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
139 * @reserved: Reserved space in message, must be 0 for backward compatibility
166 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
203 #define MSG_DEVICE_HW_STATE_OFF 0
215 * and usage of the reset flags are device specific. 0 for a bit
273 #define MSG_CLOCK_SW_STATE_UNREQ 0
316 #define MSG_CLOCK_HW_STATE_NOT_READY 0
548 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
566 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
567 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
599 * 0 - Valid bit for @dst_id
628 #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0)
656 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
709 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
710 * the destination thread is not greater than or equal to 0x8000.
738 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
739 * the destination thread is not greater than or equal to 0x8000.
771 * 0 - end of packet descriptor
784 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
826 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
865 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
948 * 0 - Return immediately
952 * 0 - the channel is split tx channel (tchan)
994 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1114 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1159 * this field are 0-255 bytes.
1209 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1312 #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)