Lines Matching full:tx
48 * written through the tx.channel pointer, while the second is only written
62 } tx; member
97 u32 tx = READ_ONCE(header->tx.count); in tegra_ivc_empty() local
110 if (tx - rx > ivc->num_frames) in tegra_ivc_empty()
113 return tx == rx; in tegra_ivc_empty()
119 u32 tx = READ_ONCE(header->tx.count); in tegra_ivc_full() local
126 return tx - rx >= ivc->num_frames; in tegra_ivc_full()
132 u32 tx = READ_ONCE(header->tx.count); in tegra_ivc_available() local
141 return tx - rx; in tegra_ivc_available()
146 WRITE_ONCE(ivc->tx.channel->tx.count, in tegra_ivc_advance_tx()
147 READ_ONCE(ivc->tx.channel->tx.count) + 1); in tegra_ivc_advance_tx()
149 if (ivc->tx.position == ivc->num_frames - 1) in tegra_ivc_advance_tx()
150 ivc->tx.position = 0; in tegra_ivc_advance_tx()
152 ivc->tx.position++; in tegra_ivc_advance_tx()
168 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_check_read()
171 * tx.channel->state is set locally, so it is not synchronized with in tegra_ivc_check_read()
178 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) in tegra_ivc_check_read()
203 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) in tegra_ivc_check_write()
206 if (!tegra_ivc_full(ivc, ivc->tx.channel)) in tegra_ivc_check_write()
209 tegra_ivc_invalidate(ivc, ivc->tx.phys + offset); in tegra_ivc_check_write()
211 if (tegra_ivc_full(ivc, ivc->tx.channel)) in tegra_ivc_check_write()
294 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_read_advance() local
312 * ivc->tx.position. in tegra_ivc_read_advance()
321 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx); in tegra_ivc_read_advance()
330 /* directly poke at the next frame to be tx'ed */
339 return tegra_ivc_frame_virt(ivc, ivc->tx.channel, ivc->tx.position); in tegra_ivc_write_get_next_frame()
343 /* advance the tx buffer */
346 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_write_advance() local
354 tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0, in tegra_ivc_write_advance()
359 * ivc->tx.position. in tegra_ivc_write_advance()
364 tegra_ivc_flush(ivc, ivc->tx.phys + tx); in tegra_ivc_write_advance()
367 * Ensure our write to ivc->tx.position occurs before our read from in tegra_ivc_write_advance()
377 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx); in tegra_ivc_write_advance()
379 if (tegra_ivc_available(ivc, ivc->tx.channel) == 1) in tegra_ivc_write_advance()
388 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_reset()
390 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_SYNC; in tegra_ivc_reset()
391 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_reset()
418 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
423 state = READ_ONCE(ivc->rx.channel->tx.state); in tegra_ivc_notified()
426 offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
430 * clearing tx.channel. in tegra_ivc_notified()
435 * Reset tx.channel counters. The remote end is in the SYNC in tegra_ivc_notified()
439 ivc->tx.channel->tx.count = 0; in tegra_ivc_notified()
442 ivc->tx.position = 0; in tegra_ivc_notified()
455 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ACK; in tegra_ivc_notified()
456 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
463 } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_SYNC && in tegra_ivc_notified()
465 offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
474 * Reset tx.channel counters. The remote end is in the ACK in tegra_ivc_notified()
478 ivc->tx.channel->tx.count = 0; in tegra_ivc_notified()
481 ivc->tx.position = 0; in tegra_ivc_notified()
495 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; in tegra_ivc_notified()
496 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
503 } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_ACK) { in tegra_ivc_notified()
504 offset = offsetof(struct tegra_ivc_header, tx.count); in tegra_ivc_notified()
509 * peer state before storing to tx.channel. in tegra_ivc_notified()
519 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; in tegra_ivc_notified()
520 tegra_ivc_flush(ivc, ivc->tx.phys + offset); in tegra_ivc_notified()
536 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) in tegra_ivc_notified()
561 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx, in tegra_ivc_check_params() argument
564 BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count), in tegra_ivc_check_params()
590 if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) { in tegra_ivc_check_params()
591 pr_err("IVC channel start not aligned: %#lx\n", tx); in tegra_ivc_check_params()
595 if (rx < tx) { in tegra_ivc_check_params()
596 if (rx + frame_size * num_frames > tx) { in tegra_ivc_check_params()
598 rx, frame_size * num_frames, tx); in tegra_ivc_check_params()
602 if (tx + frame_size * num_frames > rx) { in tegra_ivc_check_params()
604 tx, frame_size * num_frames, rx); in tegra_ivc_check_params()
613 dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys, in tegra_ivc_init() argument
631 err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx, in tegra_ivc_init()
644 ivc->tx.phys = dma_map_single(peer, tx, queue_size, in tegra_ivc_init()
646 if (dma_mapping_error(peer, ivc->tx.phys)) { in tegra_ivc_init()
653 ivc->tx.phys = tx_phys; in tegra_ivc_init()
657 ivc->tx.channel = tx; in tegra_ivc_init()
668 ivc->tx.position = 0; in tegra_ivc_init()
683 dma_unmap_single(ivc->peer, ivc->tx.phys, size, in tegra_ivc_cleanup()