Lines Matching full:dsp
3 * cs_dsp.c -- Cirrus Logic DSP firmware support
278 bool (*validate_version)(struct cs_dsp *dsp, unsigned int version);
279 unsigned int (*parse_sizes)(struct cs_dsp *dsp,
283 int (*setup_algs)(struct cs_dsp *dsp);
287 void (*show_fw_status)(struct cs_dsp *dsp);
288 void (*stop_watchdog)(struct cs_dsp *dsp);
290 int (*enable_memory)(struct cs_dsp *dsp);
291 void (*disable_memory)(struct cs_dsp *dsp);
292 int (*lock_memory)(struct cs_dsp *dsp, unsigned int lock_regions);
294 int (*enable_core)(struct cs_dsp *dsp);
295 void (*disable_core)(struct cs_dsp *dsp);
297 int (*start_core)(struct cs_dsp *dsp);
298 void (*stop_core)(struct cs_dsp *dsp);
375 static void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, const char *s) in cs_dsp_debugfs_save_wmfwname() argument
379 kfree(dsp->wmfw_file_name); in cs_dsp_debugfs_save_wmfwname()
380 dsp->wmfw_file_name = tmp; in cs_dsp_debugfs_save_wmfwname()
383 static void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, const char *s) in cs_dsp_debugfs_save_binname() argument
387 kfree(dsp->bin_file_name); in cs_dsp_debugfs_save_binname()
388 dsp->bin_file_name = tmp; in cs_dsp_debugfs_save_binname()
391 static void cs_dsp_debugfs_clear(struct cs_dsp *dsp) in cs_dsp_debugfs_clear() argument
393 kfree(dsp->wmfw_file_name); in cs_dsp_debugfs_clear()
394 kfree(dsp->bin_file_name); in cs_dsp_debugfs_clear()
395 dsp->wmfw_file_name = NULL; in cs_dsp_debugfs_clear()
396 dsp->bin_file_name = NULL; in cs_dsp_debugfs_clear()
403 struct cs_dsp *dsp = file->private_data; in cs_dsp_debugfs_wmfw_read() local
406 mutex_lock(&dsp->pwr_lock); in cs_dsp_debugfs_wmfw_read()
408 if (!dsp->wmfw_file_name || !dsp->booted) in cs_dsp_debugfs_wmfw_read()
412 dsp->wmfw_file_name, in cs_dsp_debugfs_wmfw_read()
413 strlen(dsp->wmfw_file_name)); in cs_dsp_debugfs_wmfw_read()
415 mutex_unlock(&dsp->pwr_lock); in cs_dsp_debugfs_wmfw_read()
423 struct cs_dsp *dsp = file->private_data; in cs_dsp_debugfs_bin_read() local
426 mutex_lock(&dsp->pwr_lock); in cs_dsp_debugfs_bin_read()
428 if (!dsp->bin_file_name || !dsp->booted) in cs_dsp_debugfs_bin_read()
432 dsp->bin_file_name, in cs_dsp_debugfs_bin_read()
433 strlen(dsp->bin_file_name)); in cs_dsp_debugfs_bin_read()
435 mutex_unlock(&dsp->pwr_lock); in cs_dsp_debugfs_bin_read()
460 * cs_dsp_init_debugfs() - Create and populate DSP representation in debugfs
461 * @dsp: pointer to DSP structure
462 * @debugfs_root: pointer to debugfs directory in which to create this DSP
465 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) in cs_dsp_init_debugfs() argument
470 root = debugfs_create_dir(dsp->name, debugfs_root); in cs_dsp_init_debugfs()
472 debugfs_create_bool("booted", 0444, root, &dsp->booted); in cs_dsp_init_debugfs()
473 debugfs_create_bool("running", 0444, root, &dsp->running); in cs_dsp_init_debugfs()
474 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); in cs_dsp_init_debugfs()
475 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); in cs_dsp_init_debugfs()
479 dsp, &cs_dsp_debugfs_fops[i].fops); in cs_dsp_init_debugfs()
481 dsp->debugfs_root = root; in cs_dsp_init_debugfs()
486 * cs_dsp_cleanup_debugfs() - Removes DSP representation from debugfs
487 * @dsp: pointer to DSP structure
489 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) in cs_dsp_cleanup_debugfs() argument
491 cs_dsp_debugfs_clear(dsp); in cs_dsp_cleanup_debugfs()
492 debugfs_remove_recursive(dsp->debugfs_root); in cs_dsp_cleanup_debugfs()
493 dsp->debugfs_root = NULL; in cs_dsp_cleanup_debugfs()
497 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) in cs_dsp_init_debugfs() argument
502 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) in cs_dsp_cleanup_debugfs() argument
507 static inline void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, in cs_dsp_debugfs_save_wmfwname() argument
512 static inline void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, in cs_dsp_debugfs_save_binname() argument
517 static inline void cs_dsp_debugfs_clear(struct cs_dsp *dsp) in cs_dsp_debugfs_clear() argument
522 static const struct cs_dsp_region *cs_dsp_find_region(struct cs_dsp *dsp, in cs_dsp_find_region() argument
527 for (i = 0; i < dsp->num_mems; i++) in cs_dsp_find_region()
528 if (dsp->mem[i].type == type) in cs_dsp_find_region()
529 return &dsp->mem[i]; in cs_dsp_find_region()
569 static void cs_dsp_read_fw_status(struct cs_dsp *dsp, in cs_dsp_read_fw_status() argument
576 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); in cs_dsp_read_fw_status()
578 cs_dsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); in cs_dsp_read_fw_status()
584 static void cs_dsp_adsp2_show_fw_status(struct cs_dsp *dsp) in cs_dsp_adsp2_show_fw_status() argument
590 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_adsp2_show_fw_status()
592 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_adsp2_show_fw_status()
596 static void cs_dsp_adsp2v2_show_fw_status(struct cs_dsp *dsp) in cs_dsp_adsp2v2_show_fw_status() argument
600 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_adsp2v2_show_fw_status()
602 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_adsp2v2_show_fw_status()
607 static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp) in cs_dsp_halo_show_fw_status() argument
613 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_halo_show_fw_status()
615 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_halo_show_fw_status()
623 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_base_reg() local
626 mem = cs_dsp_find_region(dsp, alg_region->type); in cs_dsp_coeff_base_reg()
628 cs_dsp_err(dsp, "No base for region %x\n", in cs_dsp_coeff_base_reg()
633 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off); in cs_dsp_coeff_base_reg()
652 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_write_acked_control() local
657 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_coeff_write_acked_control()
659 if (!dsp->running) in cs_dsp_coeff_write_acked_control()
666 cs_dsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", in cs_dsp_coeff_write_acked_control()
670 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_coeff_write_acked_control()
672 cs_dsp_err(dsp, "Failed to write %x: %d\n", reg, ret); in cs_dsp_coeff_write_acked_control()
694 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_coeff_write_acked_control()
696 cs_dsp_err(dsp, "Failed to read %x: %d\n", reg, ret); in cs_dsp_coeff_write_acked_control()
701 cs_dsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); in cs_dsp_coeff_write_acked_control()
706 cs_dsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", in cs_dsp_coeff_write_acked_control()
718 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_write_ctrl_raw() local
731 ret = regmap_raw_write(dsp->regmap, reg, scratch, in cs_dsp_coeff_write_ctrl_raw()
734 cs_dsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", in cs_dsp_coeff_write_ctrl_raw()
739 cs_dsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); in cs_dsp_coeff_write_ctrl_raw()
765 lockdep_assert_held(&ctl->dsp->pwr_lock); in cs_dsp_coeff_write_ctrl()
776 if (ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_write_ctrl()
786 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_read_ctrl_raw() local
799 ret = regmap_raw_read(dsp->regmap, reg, scratch, len); in cs_dsp_coeff_read_ctrl_raw()
801 cs_dsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", in cs_dsp_coeff_read_ctrl_raw()
806 cs_dsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); in cs_dsp_coeff_read_ctrl_raw()
833 lockdep_assert_held(&ctl->dsp->pwr_lock); in cs_dsp_coeff_read_ctrl()
839 if (ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_read_ctrl()
844 if (!ctl->flags && ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_read_ctrl()
855 static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp) in cs_dsp_coeff_init_control_caches() argument
860 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_coeff_init_control_caches()
867 * For readable controls populate the cache from the DSP memory. in cs_dsp_coeff_init_control_caches()
881 static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp) in cs_dsp_coeff_sync_controls() argument
886 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_coeff_sync_controls()
900 static void cs_dsp_signal_event_controls(struct cs_dsp *dsp, in cs_dsp_signal_event_controls() argument
906 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_signal_event_controls()
915 cs_dsp_warn(dsp, in cs_dsp_signal_event_controls()
928 static int cs_dsp_create_control(struct cs_dsp *dsp, in cs_dsp_create_control() argument
937 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_create_control()
938 if (ctl->fw_name == dsp->fw_name && in cs_dsp_create_control()
954 ctl->fw_name = dsp->fw_name; in cs_dsp_create_control()
956 if (subname && dsp->fw_ver >= 2) { in cs_dsp_create_control()
966 ctl->dsp = dsp; in cs_dsp_create_control()
978 list_add(&ctl->list, &dsp->ctl_list); in cs_dsp_create_control()
980 if (dsp->client_ops->control_add) { in cs_dsp_create_control()
981 ret = dsp->client_ops->control_add(ctl); in cs_dsp_create_control()
1059 static inline void cs_dsp_coeff_parse_alg(struct cs_dsp *dsp, const u8 **data, in cs_dsp_coeff_parse_alg() argument
1064 switch (dsp->fw_ver) { in cs_dsp_coeff_parse_alg()
1084 cs_dsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); in cs_dsp_coeff_parse_alg()
1085 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_alg()
1086 cs_dsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); in cs_dsp_coeff_parse_alg()
1089 static inline void cs_dsp_coeff_parse_coeff(struct cs_dsp *dsp, const u8 **data, in cs_dsp_coeff_parse_coeff() argument
1096 switch (dsp->fw_ver) { in cs_dsp_coeff_parse_coeff()
1127 cs_dsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); in cs_dsp_coeff_parse_coeff()
1128 cs_dsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); in cs_dsp_coeff_parse_coeff()
1129 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_coeff()
1130 cs_dsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); in cs_dsp_coeff_parse_coeff()
1131 cs_dsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); in cs_dsp_coeff_parse_coeff()
1132 cs_dsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); in cs_dsp_coeff_parse_coeff()
1135 static int cs_dsp_check_coeff_flags(struct cs_dsp *dsp, in cs_dsp_check_coeff_flags() argument
1142 cs_dsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", in cs_dsp_check_coeff_flags()
1150 static int cs_dsp_parse_coeff(struct cs_dsp *dsp, in cs_dsp_parse_coeff() argument
1159 cs_dsp_coeff_parse_alg(dsp, &data, &alg_blk); in cs_dsp_parse_coeff()
1161 cs_dsp_coeff_parse_coeff(dsp, &data, &coeff_blk); in cs_dsp_parse_coeff()
1170 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1180 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1190 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1199 cs_dsp_err(dsp, "Unknown control type: %d\n", in cs_dsp_parse_coeff()
1207 ret = cs_dsp_create_control(dsp, &alg_region, in cs_dsp_parse_coeff()
1215 cs_dsp_err(dsp, "Failed to create control: %.*s, %d\n", in cs_dsp_parse_coeff()
1222 static unsigned int cs_dsp_adsp1_parse_sizes(struct cs_dsp *dsp, in cs_dsp_adsp1_parse_sizes() argument
1231 cs_dsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, in cs_dsp_adsp1_parse_sizes()
1238 static unsigned int cs_dsp_adsp2_parse_sizes(struct cs_dsp *dsp, in cs_dsp_adsp2_parse_sizes() argument
1247 cs_dsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, in cs_dsp_adsp2_parse_sizes()
1254 static bool cs_dsp_validate_version(struct cs_dsp *dsp, unsigned int version) in cs_dsp_validate_version() argument
1258 cs_dsp_warn(dsp, "Deprecated file format %d\n", version); in cs_dsp_validate_version()
1268 static bool cs_dsp_halo_validate_version(struct cs_dsp *dsp, unsigned int version) in cs_dsp_halo_validate_version() argument
1278 static int cs_dsp_load(struct cs_dsp *dsp, const struct firmware *firmware, in cs_dsp_load() argument
1282 struct regmap *regmap = dsp->regmap; in cs_dsp_load()
1300 cs_dsp_err(dsp, "%s: file too short, %zu bytes\n", in cs_dsp_load()
1308 cs_dsp_err(dsp, "%s: invalid magic\n", file); in cs_dsp_load()
1312 if (!dsp->ops->validate_version(dsp, header->ver)) { in cs_dsp_load()
1313 cs_dsp_err(dsp, "%s: unknown file format %d\n", in cs_dsp_load()
1318 cs_dsp_info(dsp, "Firmware version: %d\n", header->ver); in cs_dsp_load()
1319 dsp->fw_ver = header->ver; in cs_dsp_load()
1321 if (header->core != dsp->type) { in cs_dsp_load()
1322 cs_dsp_err(dsp, "%s: invalid core %d != %d\n", in cs_dsp_load()
1323 file, header->core, dsp->type); in cs_dsp_load()
1328 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); in cs_dsp_load()
1334 cs_dsp_err(dsp, "%s: unexpected header length %d\n", in cs_dsp_load()
1339 cs_dsp_dbg(dsp, "%s: timestamp %llu\n", file, in cs_dsp_load()
1359 ret = cs_dsp_parse_coeff(dsp, region); in cs_dsp_load()
1380 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load()
1382 cs_dsp_err(dsp, "No region of type: %x\n", type); in cs_dsp_load()
1388 reg = dsp->ops->region_to_reg(mem, offset); in cs_dsp_load()
1391 cs_dsp_warn(dsp, in cs_dsp_load()
1397 cs_dsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, in cs_dsp_load()
1403 cs_dsp_err(dsp, in cs_dsp_load()
1413 cs_dsp_info(dsp, "%s: %s\n", file, text); in cs_dsp_load()
1423 cs_dsp_err(dsp, "Out of memory\n"); in cs_dsp_load()
1431 cs_dsp_err(dsp, in cs_dsp_load()
1446 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret); in cs_dsp_load()
1451 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", in cs_dsp_load()
1454 cs_dsp_debugfs_save_wmfwname(dsp, file); in cs_dsp_load()
1466 * @dsp: pointer to DSP structure
1475 struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type, in cs_dsp_get_ctl() argument
1480 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_get_ctl()
1482 list_for_each_entry(pos, &dsp->ctl_list, list) { in cs_dsp_get_ctl()
1486 pos->fw_name == dsp->fw_name && in cs_dsp_get_ctl()
1498 static void cs_dsp_ctl_fixup_base(struct cs_dsp *dsp, in cs_dsp_ctl_fixup_base() argument
1503 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_ctl_fixup_base()
1504 if (ctl->fw_name == dsp->fw_name && in cs_dsp_ctl_fixup_base()
1512 static void *cs_dsp_read_algs(struct cs_dsp *dsp, size_t n_algs, in cs_dsp_read_algs() argument
1522 cs_dsp_err(dsp, "No algorithms\n"); in cs_dsp_read_algs()
1527 cs_dsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); in cs_dsp_read_algs()
1532 reg = dsp->ops->region_to_reg(mem, pos + len); in cs_dsp_read_algs()
1534 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_read_algs()
1536 cs_dsp_err(dsp, "Failed to read algorithm list end: %d\n", in cs_dsp_read_algs()
1542 cs_dsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", in cs_dsp_read_algs()
1545 /* Convert length from DSP words to bytes */ in cs_dsp_read_algs()
1552 reg = dsp->ops->region_to_reg(mem, pos); in cs_dsp_read_algs()
1554 ret = regmap_raw_read(dsp->regmap, reg, alg, len); in cs_dsp_read_algs()
1556 cs_dsp_err(dsp, "Failed to read algorithm list: %d\n", ret); in cs_dsp_read_algs()
1566 * @dsp: pointer to DSP structure
1572 struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, in cs_dsp_find_alg_region() argument
1577 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_find_alg_region()
1579 list_for_each_entry(alg_region, &dsp->alg_regions, list) { in cs_dsp_find_alg_region()
1588 static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp, in cs_dsp_create_region() argument
1603 list_add_tail(&alg_region->list, &dsp->alg_regions); in cs_dsp_create_region()
1605 if (dsp->fw_ver > 0) in cs_dsp_create_region()
1606 cs_dsp_ctl_fixup_base(dsp, alg_region); in cs_dsp_create_region()
1611 static void cs_dsp_free_alg_regions(struct cs_dsp *dsp) in cs_dsp_free_alg_regions() argument
1615 while (!list_empty(&dsp->alg_regions)) { in cs_dsp_free_alg_regions()
1616 alg_region = list_first_entry(&dsp->alg_regions, in cs_dsp_free_alg_regions()
1624 static void cs_dsp_parse_wmfw_id_header(struct cs_dsp *dsp, in cs_dsp_parse_wmfw_id_header() argument
1627 dsp->fw_id = be32_to_cpu(fw->id); in cs_dsp_parse_wmfw_id_header()
1628 dsp->fw_id_version = be32_to_cpu(fw->ver); in cs_dsp_parse_wmfw_id_header()
1630 cs_dsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", in cs_dsp_parse_wmfw_id_header()
1631 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, in cs_dsp_parse_wmfw_id_header()
1632 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, in cs_dsp_parse_wmfw_id_header()
1636 static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp, in cs_dsp_parse_wmfw_v3_id_header() argument
1639 dsp->fw_id = be32_to_cpu(fw->id); in cs_dsp_parse_wmfw_v3_id_header()
1640 dsp->fw_id_version = be32_to_cpu(fw->ver); in cs_dsp_parse_wmfw_v3_id_header()
1641 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); in cs_dsp_parse_wmfw_v3_id_header()
1643 cs_dsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", in cs_dsp_parse_wmfw_v3_id_header()
1644 dsp->fw_id, dsp->fw_vendor_id, in cs_dsp_parse_wmfw_v3_id_header()
1645 (dsp->fw_id_version & 0xff0000) >> 16, in cs_dsp_parse_wmfw_v3_id_header()
1646 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, in cs_dsp_parse_wmfw_v3_id_header()
1650 static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, in cs_dsp_create_regions() argument
1657 alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]); in cs_dsp_create_regions()
1665 static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp) in cs_dsp_adsp1_setup_algs() argument
1675 mem = cs_dsp_find_region(dsp, WMFW_ADSP1_DM); in cs_dsp_adsp1_setup_algs()
1679 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, in cs_dsp_adsp1_setup_algs()
1682 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_adsp1_setup_algs()
1689 cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs); in cs_dsp_adsp1_setup_algs()
1691 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, in cs_dsp_adsp1_setup_algs()
1697 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, in cs_dsp_adsp1_setup_algs()
1703 /* Calculate offset and length in DSP words */ in cs_dsp_adsp1_setup_algs()
1707 adsp1_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_adsp1_setup_algs()
1712 cs_dsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", in cs_dsp_adsp1_setup_algs()
1720 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, in cs_dsp_adsp1_setup_algs()
1728 if (dsp->fw_ver == 0) { in cs_dsp_adsp1_setup_algs()
1733 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp1_setup_algs()
1737 cs_dsp_warn(dsp, "Missing length info for region DM with ID %x\n", in cs_dsp_adsp1_setup_algs()
1742 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, in cs_dsp_adsp1_setup_algs()
1750 if (dsp->fw_ver == 0) { in cs_dsp_adsp1_setup_algs()
1755 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp1_setup_algs()
1759 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", in cs_dsp_adsp1_setup_algs()
1770 static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp) in cs_dsp_adsp2_setup_algs() argument
1780 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); in cs_dsp_adsp2_setup_algs()
1784 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, in cs_dsp_adsp2_setup_algs()
1787 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_adsp2_setup_algs()
1794 cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs); in cs_dsp_adsp2_setup_algs()
1796 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, in cs_dsp_adsp2_setup_algs()
1802 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, in cs_dsp_adsp2_setup_algs()
1808 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, in cs_dsp_adsp2_setup_algs()
1814 /* Calculate offset and length in DSP words */ in cs_dsp_adsp2_setup_algs()
1818 adsp2_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_adsp2_setup_algs()
1823 cs_dsp_info(dsp, in cs_dsp_adsp2_setup_algs()
1833 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, in cs_dsp_adsp2_setup_algs()
1841 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1846 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1850 cs_dsp_warn(dsp, "Missing length info for region XM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1855 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, in cs_dsp_adsp2_setup_algs()
1863 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1868 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1872 cs_dsp_warn(dsp, "Missing length info for region YM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1877 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, in cs_dsp_adsp2_setup_algs()
1885 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1890 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1894 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1905 static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, in cs_dsp_halo_create_regions() argument
1914 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); in cs_dsp_halo_create_regions()
1917 static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp) in cs_dsp_halo_setup_algs() argument
1926 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); in cs_dsp_halo_setup_algs()
1930 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, in cs_dsp_halo_setup_algs()
1933 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_halo_setup_algs()
1940 cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs); in cs_dsp_halo_setup_algs()
1942 ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver, in cs_dsp_halo_setup_algs()
1947 /* Calculate offset and length in DSP words */ in cs_dsp_halo_setup_algs()
1951 halo_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_halo_setup_algs()
1956 cs_dsp_info(dsp, in cs_dsp_halo_setup_algs()
1965 ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id, in cs_dsp_halo_setup_algs()
1978 static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware, in cs_dsp_load_coeff() argument
1982 struct regmap *regmap = dsp->regmap; in cs_dsp_load_coeff()
1998 cs_dsp_err(dsp, "%s: coefficient file too short, %zu bytes\n", in cs_dsp_load_coeff()
2005 cs_dsp_err(dsp, "%s: invalid coefficient magic\n", file); in cs_dsp_load_coeff()
2014 cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n", in cs_dsp_load_coeff()
2020 cs_dsp_dbg(dsp, "%s: v%d.%d.%d\n", file, in cs_dsp_load_coeff()
2036 cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", in cs_dsp_load_coeff()
2041 cs_dsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", in cs_dsp_load_coeff()
2058 if (le32_to_cpu(blk->id) == dsp->fw_id && in cs_dsp_load_coeff()
2061 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load_coeff()
2063 cs_dsp_err(dsp, "No ZM\n"); in cs_dsp_load_coeff()
2066 reg = dsp->ops->region_to_reg(mem, 0); in cs_dsp_load_coeff()
2081 cs_dsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", in cs_dsp_load_coeff()
2085 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load_coeff()
2087 cs_dsp_err(dsp, "No base for region %x\n", type); in cs_dsp_load_coeff()
2091 alg_region = cs_dsp_find_alg_region(dsp, type, in cs_dsp_load_coeff()
2095 cs_dsp_warn(dsp, in cs_dsp_load_coeff()
2105 reg = dsp->ops->region_to_reg(mem, reg); in cs_dsp_load_coeff()
2108 cs_dsp_err(dsp, "No %x for algorithm %x\n", in cs_dsp_load_coeff()
2114 cs_dsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", in cs_dsp_load_coeff()
2121 cs_dsp_info(dsp, "%s: %s\n", dsp->fw_name, text); in cs_dsp_load_coeff()
2129 cs_dsp_err(dsp, in cs_dsp_load_coeff()
2142 cs_dsp_err(dsp, "Out of memory\n"); in cs_dsp_load_coeff()
2147 cs_dsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", in cs_dsp_load_coeff()
2153 cs_dsp_err(dsp, in cs_dsp_load_coeff()
2165 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret); in cs_dsp_load_coeff()
2168 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", in cs_dsp_load_coeff()
2171 cs_dsp_debugfs_save_binname(dsp, file); in cs_dsp_load_coeff()
2180 static int cs_dsp_create_name(struct cs_dsp *dsp) in cs_dsp_create_name() argument
2182 if (!dsp->name) { in cs_dsp_create_name()
2183 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", in cs_dsp_create_name()
2184 dsp->num); in cs_dsp_create_name()
2185 if (!dsp->name) in cs_dsp_create_name()
2192 static int cs_dsp_common_init(struct cs_dsp *dsp) in cs_dsp_common_init() argument
2196 ret = cs_dsp_create_name(dsp); in cs_dsp_common_init()
2200 INIT_LIST_HEAD(&dsp->alg_regions); in cs_dsp_common_init()
2201 INIT_LIST_HEAD(&dsp->ctl_list); in cs_dsp_common_init()
2203 mutex_init(&dsp->pwr_lock); in cs_dsp_common_init()
2210 * @dsp: pointer to DSP structure
2214 int cs_dsp_adsp1_init(struct cs_dsp *dsp) in cs_dsp_adsp1_init() argument
2216 dsp->ops = &cs_dsp_adsp1_ops; in cs_dsp_adsp1_init()
2218 return cs_dsp_common_init(dsp); in cs_dsp_adsp1_init()
2224 * @dsp: pointer to DSP structure
2233 int cs_dsp_adsp1_power_up(struct cs_dsp *dsp, in cs_dsp_adsp1_power_up() argument
2241 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2243 dsp->fw_name = fw_name; in cs_dsp_adsp1_power_up()
2245 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2249 * For simplicity set the DSP clock rate to be the in cs_dsp_adsp1_power_up()
2252 if (dsp->sysclk_reg) { in cs_dsp_adsp1_power_up()
2253 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); in cs_dsp_adsp1_power_up()
2255 cs_dsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); in cs_dsp_adsp1_power_up()
2259 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; in cs_dsp_adsp1_power_up()
2261 ret = regmap_update_bits(dsp->regmap, in cs_dsp_adsp1_power_up()
2262 dsp->base + ADSP1_CONTROL_31, in cs_dsp_adsp1_power_up()
2265 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); in cs_dsp_adsp1_power_up()
2270 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); in cs_dsp_adsp1_power_up()
2274 ret = cs_dsp_adsp1_setup_algs(dsp); in cs_dsp_adsp1_power_up()
2278 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); in cs_dsp_adsp1_power_up()
2283 ret = cs_dsp_coeff_init_control_caches(dsp); in cs_dsp_adsp1_power_up()
2288 ret = cs_dsp_coeff_sync_controls(dsp); in cs_dsp_adsp1_power_up()
2292 dsp->booted = true; in cs_dsp_adsp1_power_up()
2295 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2299 dsp->running = true; in cs_dsp_adsp1_power_up()
2301 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2306 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2309 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2315 * cs_dsp_adsp1_power_down() - Halts the DSP
2316 * @dsp: pointer to DSP structure
2318 void cs_dsp_adsp1_power_down(struct cs_dsp *dsp) in cs_dsp_adsp1_power_down() argument
2322 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp1_power_down()
2324 dsp->running = false; in cs_dsp_adsp1_power_down()
2325 dsp->booted = false; in cs_dsp_adsp1_power_down()
2328 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_down()
2331 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, in cs_dsp_adsp1_power_down()
2334 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_down()
2337 list_for_each_entry(ctl, &dsp->ctl_list, list) in cs_dsp_adsp1_power_down()
2340 cs_dsp_free_alg_regions(dsp); in cs_dsp_adsp1_power_down()
2342 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_down()
2346 static int cs_dsp_adsp2v2_enable_core(struct cs_dsp *dsp) in cs_dsp_adsp2v2_enable_core() argument
2353 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); in cs_dsp_adsp2v2_enable_core()
2364 cs_dsp_err(dsp, "Failed to start DSP RAM\n"); in cs_dsp_adsp2v2_enable_core()
2368 cs_dsp_dbg(dsp, "RAM ready after %d polls\n", count); in cs_dsp_adsp2v2_enable_core()
2373 static int cs_dsp_adsp2_enable_core(struct cs_dsp *dsp) in cs_dsp_adsp2_enable_core() argument
2377 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_enable_core()
2382 return cs_dsp_adsp2v2_enable_core(dsp); in cs_dsp_adsp2_enable_core()
2385 static int cs_dsp_adsp2_lock(struct cs_dsp *dsp, unsigned int lock_regions) in cs_dsp_adsp2_lock() argument
2387 struct regmap *regmap = dsp->regmap; in cs_dsp_adsp2_lock()
2394 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; in cs_dsp_adsp2_lock()
2415 static int cs_dsp_adsp2_enable_memory(struct cs_dsp *dsp) in cs_dsp_adsp2_enable_memory() argument
2417 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_enable_memory()
2421 static void cs_dsp_adsp2_disable_memory(struct cs_dsp *dsp) in cs_dsp_adsp2_disable_memory() argument
2423 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_disable_memory()
2427 static void cs_dsp_adsp2_disable_core(struct cs_dsp *dsp) in cs_dsp_adsp2_disable_core() argument
2429 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); in cs_dsp_adsp2_disable_core()
2430 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); in cs_dsp_adsp2_disable_core()
2431 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); in cs_dsp_adsp2_disable_core()
2433 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_disable_core()
2437 static void cs_dsp_adsp2v2_disable_core(struct cs_dsp *dsp) in cs_dsp_adsp2v2_disable_core() argument
2439 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); in cs_dsp_adsp2v2_disable_core()
2440 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); in cs_dsp_adsp2v2_disable_core()
2441 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); in cs_dsp_adsp2v2_disable_core()
2444 static int cs_dsp_halo_configure_mpu(struct cs_dsp *dsp, unsigned int lock_regions) in cs_dsp_halo_configure_mpu() argument
2447 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, in cs_dsp_halo_configure_mpu()
2448 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, in cs_dsp_halo_configure_mpu()
2449 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2450 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2451 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2452 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2453 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2454 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2455 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2456 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2457 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2458 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2459 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2460 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2461 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2462 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2463 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2464 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2465 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2466 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2467 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2468 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2469 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, in cs_dsp_halo_configure_mpu()
2472 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); in cs_dsp_halo_configure_mpu()
2477 * @dsp: pointer to DSP structure
2484 int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq) in cs_dsp_set_dspclk() argument
2488 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, in cs_dsp_set_dspclk()
2492 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); in cs_dsp_set_dspclk()
2498 static void cs_dsp_stop_watchdog(struct cs_dsp *dsp) in cs_dsp_stop_watchdog() argument
2500 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, in cs_dsp_stop_watchdog()
2504 static void cs_dsp_halo_stop_watchdog(struct cs_dsp *dsp) in cs_dsp_halo_stop_watchdog() argument
2506 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, in cs_dsp_halo_stop_watchdog()
2511 * cs_dsp_power_up() - Downloads firmware to the DSP
2512 * @dsp: pointer to DSP structure
2519 * This function is used on ADSP2 and Halo DSP cores, it powers-up the DSP core
2527 int cs_dsp_power_up(struct cs_dsp *dsp, in cs_dsp_power_up() argument
2534 mutex_lock(&dsp->pwr_lock); in cs_dsp_power_up()
2536 dsp->fw_name = fw_name; in cs_dsp_power_up()
2538 if (dsp->ops->enable_memory) { in cs_dsp_power_up()
2539 ret = dsp->ops->enable_memory(dsp); in cs_dsp_power_up()
2544 if (dsp->ops->enable_core) { in cs_dsp_power_up()
2545 ret = dsp->ops->enable_core(dsp); in cs_dsp_power_up()
2550 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); in cs_dsp_power_up()
2554 ret = dsp->ops->setup_algs(dsp); in cs_dsp_power_up()
2558 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); in cs_dsp_power_up()
2563 ret = cs_dsp_coeff_init_control_caches(dsp); in cs_dsp_power_up()
2567 if (dsp->ops->disable_core) in cs_dsp_power_up()
2568 dsp->ops->disable_core(dsp); in cs_dsp_power_up()
2570 dsp->booted = true; in cs_dsp_power_up()
2572 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_up()
2576 if (dsp->ops->disable_core) in cs_dsp_power_up()
2577 dsp->ops->disable_core(dsp); in cs_dsp_power_up()
2579 if (dsp->ops->disable_memory) in cs_dsp_power_up()
2580 dsp->ops->disable_memory(dsp); in cs_dsp_power_up()
2582 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_up()
2589 * cs_dsp_power_down() - Powers-down the DSP
2590 * @dsp: pointer to DSP structure
2595 void cs_dsp_power_down(struct cs_dsp *dsp) in cs_dsp_power_down() argument
2599 mutex_lock(&dsp->pwr_lock); in cs_dsp_power_down()
2601 cs_dsp_debugfs_clear(dsp); in cs_dsp_power_down()
2603 dsp->fw_id = 0; in cs_dsp_power_down()
2604 dsp->fw_id_version = 0; in cs_dsp_power_down()
2606 dsp->booted = false; in cs_dsp_power_down()
2608 if (dsp->ops->disable_memory) in cs_dsp_power_down()
2609 dsp->ops->disable_memory(dsp); in cs_dsp_power_down()
2611 list_for_each_entry(ctl, &dsp->ctl_list, list) in cs_dsp_power_down()
2614 cs_dsp_free_alg_regions(dsp); in cs_dsp_power_down()
2616 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_down()
2618 cs_dsp_dbg(dsp, "Shutdown complete\n"); in cs_dsp_power_down()
2622 static int cs_dsp_adsp2_start_core(struct cs_dsp *dsp) in cs_dsp_adsp2_start_core() argument
2624 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_start_core()
2629 static void cs_dsp_adsp2_stop_core(struct cs_dsp *dsp) in cs_dsp_adsp2_stop_core() argument
2631 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_stop_core()
2637 * @dsp: pointer to DSP structure
2643 int cs_dsp_run(struct cs_dsp *dsp) in cs_dsp_run() argument
2647 mutex_lock(&dsp->pwr_lock); in cs_dsp_run()
2649 if (!dsp->booted) { in cs_dsp_run()
2654 if (dsp->ops->enable_core) { in cs_dsp_run()
2655 ret = dsp->ops->enable_core(dsp); in cs_dsp_run()
2660 if (dsp->client_ops->pre_run) { in cs_dsp_run()
2661 ret = dsp->client_ops->pre_run(dsp); in cs_dsp_run()
2667 ret = cs_dsp_coeff_sync_controls(dsp); in cs_dsp_run()
2671 if (dsp->ops->lock_memory) { in cs_dsp_run()
2672 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); in cs_dsp_run()
2674 cs_dsp_err(dsp, "Error configuring MPU: %d\n", ret); in cs_dsp_run()
2679 if (dsp->ops->start_core) { in cs_dsp_run()
2680 ret = dsp->ops->start_core(dsp); in cs_dsp_run()
2685 dsp->running = true; in cs_dsp_run()
2687 if (dsp->client_ops->post_run) { in cs_dsp_run()
2688 ret = dsp->client_ops->post_run(dsp); in cs_dsp_run()
2693 mutex_unlock(&dsp->pwr_lock); in cs_dsp_run()
2698 if (dsp->ops->stop_core) in cs_dsp_run()
2699 dsp->ops->stop_core(dsp); in cs_dsp_run()
2700 if (dsp->ops->disable_core) in cs_dsp_run()
2701 dsp->ops->disable_core(dsp); in cs_dsp_run()
2702 mutex_unlock(&dsp->pwr_lock); in cs_dsp_run()
2710 * @dsp: pointer to DSP structure
2714 void cs_dsp_stop(struct cs_dsp *dsp) in cs_dsp_stop() argument
2717 cs_dsp_signal_event_controls(dsp, CS_DSP_FW_EVENT_SHUTDOWN); in cs_dsp_stop()
2719 if (dsp->ops->stop_watchdog) in cs_dsp_stop()
2720 dsp->ops->stop_watchdog(dsp); in cs_dsp_stop()
2723 if (dsp->ops->show_fw_status) in cs_dsp_stop()
2724 dsp->ops->show_fw_status(dsp); in cs_dsp_stop()
2726 mutex_lock(&dsp->pwr_lock); in cs_dsp_stop()
2728 if (dsp->client_ops->pre_stop) in cs_dsp_stop()
2729 dsp->client_ops->pre_stop(dsp); in cs_dsp_stop()
2731 dsp->running = false; in cs_dsp_stop()
2733 if (dsp->ops->stop_core) in cs_dsp_stop()
2734 dsp->ops->stop_core(dsp); in cs_dsp_stop()
2735 if (dsp->ops->disable_core) in cs_dsp_stop()
2736 dsp->ops->disable_core(dsp); in cs_dsp_stop()
2738 if (dsp->client_ops->post_stop) in cs_dsp_stop()
2739 dsp->client_ops->post_stop(dsp); in cs_dsp_stop()
2741 mutex_unlock(&dsp->pwr_lock); in cs_dsp_stop()
2743 cs_dsp_dbg(dsp, "Execution stopped\n"); in cs_dsp_stop()
2747 static int cs_dsp_halo_start_core(struct cs_dsp *dsp) in cs_dsp_halo_start_core() argument
2751 ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_start_core()
2757 return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_start_core()
2761 static void cs_dsp_halo_stop_core(struct cs_dsp *dsp) in cs_dsp_halo_stop_core() argument
2763 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_stop_core()
2767 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, in cs_dsp_halo_stop_core()
2773 * @dsp: pointer to DSP structure
2777 int cs_dsp_adsp2_init(struct cs_dsp *dsp) in cs_dsp_adsp2_init() argument
2781 switch (dsp->rev) { in cs_dsp_adsp2_init()
2784 * Disable the DSP memory by default when in reset for a small in cs_dsp_adsp2_init()
2787 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_init()
2790 cs_dsp_err(dsp, in cs_dsp_adsp2_init()
2795 dsp->ops = &cs_dsp_adsp2_ops[0]; in cs_dsp_adsp2_init()
2798 dsp->ops = &cs_dsp_adsp2_ops[1]; in cs_dsp_adsp2_init()
2801 dsp->ops = &cs_dsp_adsp2_ops[2]; in cs_dsp_adsp2_init()
2805 return cs_dsp_common_init(dsp); in cs_dsp_adsp2_init()
2810 * cs_dsp_halo_init() - Initialise a cs_dsp structure representing a HALO Core DSP
2811 * @dsp: pointer to DSP structure
2815 int cs_dsp_halo_init(struct cs_dsp *dsp) in cs_dsp_halo_init() argument
2817 dsp->ops = &cs_dsp_halo_ops; in cs_dsp_halo_init()
2819 return cs_dsp_common_init(dsp); in cs_dsp_halo_init()
2825 * @dsp: pointer to DSP structure
2827 void cs_dsp_remove(struct cs_dsp *dsp) in cs_dsp_remove() argument
2831 while (!list_empty(&dsp->ctl_list)) { in cs_dsp_remove()
2832 ctl = list_first_entry(&dsp->ctl_list, struct cs_dsp_coeff_ctl, list); in cs_dsp_remove()
2834 if (dsp->client_ops->control_remove) in cs_dsp_remove()
2835 dsp->client_ops->control_remove(ctl); in cs_dsp_remove()
2844 * cs_dsp_read_raw_data_block() - Reads a block of data from DSP memory
2845 * @dsp: pointer to DSP structure
2846 * @mem_type: the type of DSP memory containing the data to be read
2851 * If this is used to read unpacked 24-bit memory, each 24-bit DSP word will
2857 int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, in cs_dsp_read_raw_data_block() argument
2860 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); in cs_dsp_read_raw_data_block()
2864 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_read_raw_data_block()
2869 reg = dsp->ops->region_to_reg(mem, mem_addr); in cs_dsp_read_raw_data_block()
2871 ret = regmap_raw_read(dsp->regmap, reg, data, in cs_dsp_read_raw_data_block()
2881 * cs_dsp_read_data_word() - Reads a word from DSP memory
2882 * @dsp: pointer to DSP structure
2883 * @mem_type: the type of DSP memory containing the data to be read
2889 int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data) in cs_dsp_read_data_word() argument
2894 ret = cs_dsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw); in cs_dsp_read_data_word()
2905 * cs_dsp_write_data_word() - Writes a word to DSP memory
2906 * @dsp: pointer to DSP structure
2907 * @mem_type: the type of DSP memory containing the data to be written
2913 int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data) in cs_dsp_write_data_word() argument
2915 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); in cs_dsp_write_data_word()
2919 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_write_data_word()
2924 reg = dsp->ops->region_to_reg(mem, mem_addr); in cs_dsp_write_data_word()
2926 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_write_data_word()
2932 * @buf: buffer containing DSP words read from DSP memory
2935 * DSP words from the register map have pad bytes and the data bytes
2955 * cs_dsp_adsp2_bus_error() - Handle a DSP bus error interrupt
2956 * @dsp: pointer to DSP structure
2958 * The firmware and DSP state will be logged for future analysis.
2960 void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp) in cs_dsp_adsp2_bus_error() argument
2963 struct regmap *regmap = dsp->regmap; in cs_dsp_adsp2_bus_error()
2966 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp2_bus_error()
2968 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); in cs_dsp_adsp2_bus_error()
2970 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
2976 cs_dsp_err(dsp, "watchdog timeout error\n"); in cs_dsp_adsp2_bus_error()
2977 dsp->ops->stop_watchdog(dsp); in cs_dsp_adsp2_bus_error()
2978 if (dsp->client_ops->watchdog_expired) in cs_dsp_adsp2_bus_error()
2979 dsp->client_ops->watchdog_expired(dsp); in cs_dsp_adsp2_bus_error()
2984 cs_dsp_err(dsp, "bus error: address error\n"); in cs_dsp_adsp2_bus_error()
2986 cs_dsp_err(dsp, "bus error: region lock error\n"); in cs_dsp_adsp2_bus_error()
2988 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); in cs_dsp_adsp2_bus_error()
2990 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
2996 cs_dsp_err(dsp, "bus error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3000 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, in cs_dsp_adsp2_bus_error()
3003 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
3009 cs_dsp_err(dsp, "xmem error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3011 cs_dsp_err(dsp, "pmem error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3016 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, in cs_dsp_adsp2_bus_error()
3020 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp2_bus_error()
3025 * cs_dsp_halo_bus_error() - Handle a DSP bus error interrupt
3026 * @dsp: pointer to DSP structure
3028 * The firmware and DSP state will be logged for future analysis.
3030 void cs_dsp_halo_bus_error(struct cs_dsp *dsp) in cs_dsp_halo_bus_error() argument
3032 struct regmap *regmap = dsp->regmap; in cs_dsp_halo_bus_error()
3035 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3036 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3037 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3041 mutex_lock(&dsp->pwr_lock); in cs_dsp_halo_bus_error()
3043 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, in cs_dsp_halo_bus_error()
3046 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); in cs_dsp_halo_bus_error()
3050 cs_dsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", in cs_dsp_halo_bus_error()
3055 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, in cs_dsp_halo_bus_error()
3058 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); in cs_dsp_halo_bus_error()
3062 cs_dsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); in cs_dsp_halo_bus_error()
3064 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, in cs_dsp_halo_bus_error()
3067 cs_dsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); in cs_dsp_halo_bus_error()
3071 cs_dsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); in cs_dsp_halo_bus_error()
3072 cs_dsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); in cs_dsp_halo_bus_error()
3073 cs_dsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); in cs_dsp_halo_bus_error()
3075 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); in cs_dsp_halo_bus_error()
3077 cs_dsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); in cs_dsp_halo_bus_error()
3080 mutex_unlock(&dsp->pwr_lock); in cs_dsp_halo_bus_error()
3085 * cs_dsp_halo_wdt_expire() - Handle DSP watchdog expiry
3086 * @dsp: pointer to DSP structure
3090 void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp) in cs_dsp_halo_wdt_expire() argument
3092 mutex_lock(&dsp->pwr_lock); in cs_dsp_halo_wdt_expire()
3094 cs_dsp_warn(dsp, "WDT Expiry Fault\n"); in cs_dsp_halo_wdt_expire()
3096 dsp->ops->stop_watchdog(dsp); in cs_dsp_halo_wdt_expire()
3097 if (dsp->client_ops->watchdog_expired) in cs_dsp_halo_wdt_expire()
3098 dsp->client_ops->watchdog_expired(dsp); in cs_dsp_halo_wdt_expire()
3100 mutex_unlock(&dsp->pwr_lock); in cs_dsp_halo_wdt_expire()
3184 * cs_dsp_chunk_write() - Format data to a DSP memory chunk
3189 * This function sequentially writes values into the format required for DSP
3191 * big endian. Note that data is only committed to the chunk when a whole DSP
3230 * As cs_dsp_chunk_write only writes data when a whole DSP word is ready to
3232 * function will pad that data with zeros upto a whole DSP word and write out.
3246 * cs_dsp_chunk_read() - Parse data from a DSP memory chunk
3250 * This function sequentially reads values from a DSP memory formatted buffer,
3287 MODULE_DESCRIPTION("Cirrus Logic DSP Support");