Lines Matching +full:zynq +full:- +full:ddrc +full:- +full:a05
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
199 /* DDRC Software control register */
202 /* DDRC ECC CE & UE poison mask */
206 /* DDRC Device config masks */
267 * struct ecc_error_info - ECC error log information.
287 * struct synps_ecc_status - ECC status information to report.
301 * struct synps_edac_priv - DDR memory controller private instance data.
333 * struct synps_platform_data - synps platform data structure.
349 * zynq_get_error_info - Get the current ECC error info.
360 base = priv->baseaddr; in zynq_get_error_info()
361 p = &priv->stat; in zynq_get_error_info()
367 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
368 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
371 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
374 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
376 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
377 p->ceinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
378 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
379 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in zynq_get_error_info()
380 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, in zynq_get_error_info()
381 p->ceinfo.data); in zynq_get_error_info()
386 if (!(p->ue_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
390 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
391 p->ueinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
392 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
393 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in zynq_get_error_info()
404 * zynqmp_get_error_info - Get the current ECC error info.
415 base = priv->baseaddr; in zynqmp_get_error_info()
416 p = &priv->stat; in zynqmp_get_error_info()
419 p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; in zynqmp_get_error_info()
420 p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; in zynqmp_get_error_info()
421 if (!p->ce_cnt) in zynqmp_get_error_info()
428 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); in zynqmp_get_error_info()
431 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
433 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
435 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
437 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
438 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); in zynqmp_get_error_info()
443 if (!p->ue_cnt) in zynqmp_get_error_info()
447 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
449 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
451 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
453 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
454 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); in zynqmp_get_error_info()
465 * handle_error - Handle Correctable and Uncorrectable errors.
473 struct synps_edac_priv *priv = mci->pvt_info; in handle_error()
476 if (p->ce_cnt) { in handle_error()
477 pinf = &p->ceinfo; in handle_error()
478 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
479 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
481 "CE", pinf->row, pinf->bank, in handle_error()
482 pinf->bankgrpnr, pinf->blknr, in handle_error()
483 pinf->bitpos, pinf->data); in handle_error()
485 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
487 "CE", pinf->row, pinf->bank, pinf->col, in handle_error()
488 pinf->bitpos, pinf->data); in handle_error()
492 p->ce_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
493 priv->message, ""); in handle_error()
496 if (p->ue_cnt) { in handle_error()
497 pinf = &p->ueinfo; in handle_error()
498 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
499 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
501 "UE", pinf->row, pinf->bank, in handle_error()
502 pinf->bankgrpnr, pinf->blknr); in handle_error()
504 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
506 "UE", pinf->row, pinf->bank, pinf->col); in handle_error()
510 p->ue_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
511 priv->message, ""); in handle_error()
520 if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) in enable_intr()
522 priv->baseaddr + ECC_CLR_OFST); in enable_intr()
525 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); in enable_intr()
532 if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) in disable_intr()
533 writel(0x0, priv->baseaddr + ECC_CLR_OFST); in disable_intr()
536 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); in disable_intr()
540 * intr_handler - Interrupt Handler for ECC interrupts.
553 priv = mci->pvt_info; in intr_handler()
554 p_data = priv->p_data; in intr_handler()
560 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in intr_handler()
561 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
567 status = p_data->get_error_info(priv); in intr_handler()
571 priv->ce_cnt += priv->stat.ce_cnt; in intr_handler()
572 priv->ue_cnt += priv->stat.ue_cnt; in intr_handler()
573 handle_error(mci, &priv->stat); in intr_handler()
576 priv->ce_cnt, priv->ue_cnt); in intr_handler()
578 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) in intr_handler()
579 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
587 * check_errors - Check controller for ECC errors.
598 priv = mci->pvt_info; in check_errors()
599 p_data = priv->p_data; in check_errors()
601 status = p_data->get_error_info(priv); in check_errors()
605 priv->ce_cnt += priv->stat.ce_cnt; in check_errors()
606 priv->ue_cnt += priv->stat.ue_cnt; in check_errors()
607 handle_error(mci, &priv->stat); in check_errors()
610 priv->ce_cnt, priv->ue_cnt); in check_errors()
614 * zynq_get_dtype - Return the controller memory width.
645 * zynqmp_get_dtype - Return the controller memory width.
678 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
702 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
707 * Return: a ECC status boolean i.e true/false - enabled/disabled.
727 * get_memsize - Read the size of the attached memory device.
741 * zynq_get_mtype - Return the controller memory type.
765 * zynqmp_get_mtype - Returns controller memory type.
793 * init_csrows - Initialize the csrow data.
801 struct synps_edac_priv *priv = mci->pvt_info; in init_csrows()
808 p_data = priv->p_data; in init_csrows()
810 for (row = 0; row < mci->nr_csrows; row++) { in init_csrows()
811 csi = mci->csrows[row]; in init_csrows()
814 for (j = 0; j < csi->nr_channels; j++) { in init_csrows()
815 dimm = csi->channels[j]->dimm; in init_csrows()
816 dimm->edac_mode = EDAC_SECDED; in init_csrows()
817 dimm->mtype = p_data->get_mtype(priv->baseaddr); in init_csrows()
818 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; in init_csrows()
819 dimm->grain = SYNPS_EDAC_ERR_GRAIN; in init_csrows()
820 dimm->dtype = p_data->get_dtype(priv->baseaddr); in init_csrows()
826 * mc_init - Initialize one driver instance.
831 * related driver-private data associated with the memory controller the
838 mci->pdev = &pdev->dev; in mc_init()
839 priv = mci->pvt_info; in mc_init()
843 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; in mc_init()
844 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in mc_init()
845 mci->scrub_cap = SCRUB_HW_SRC; in mc_init()
846 mci->scrub_mode = SCRUB_NONE; in mc_init()
848 mci->edac_cap = EDAC_FLAG_SECDED; in mc_init()
849 mci->ctl_name = "synps_ddr_controller"; in mc_init()
850 mci->dev_name = SYNPS_EDAC_MOD_STRING; in mc_init()
851 mci->mod_name = SYNPS_EDAC_MOD_VER; in mc_init()
853 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_init()
857 mci->edac_check = check_errors; in mc_init()
860 mci->ctl_page_to_phys = NULL; in mc_init()
868 struct synps_edac_priv *priv = mci->pvt_info; in setup_irq()
878 ret = devm_request_irq(&pdev->dev, irq, intr_handler, in setup_irq()
879 0, dev_name(&pdev->dev), mci); in setup_irq()
925 .compatible = "xlnx,zynq-ddrc-a05",
929 .compatible = "xlnx,zynqmp-ddrc-2.40a",
933 .compatible = "snps,ddrc-3.80a",
947 * ddr_poison_setup - Update poison registers.
959 hif_addr = priv->poison_addr >> 3; in ddr_poison_setup()
962 if (priv->row_shift[index]) in ddr_poison_setup()
963 row |= (((hif_addr >> priv->row_shift[index]) & in ddr_poison_setup()
970 if (priv->col_shift[index] || index < 3) in ddr_poison_setup()
971 col |= (((hif_addr >> priv->col_shift[index]) & in ddr_poison_setup()
978 if (priv->bank_shift[index]) in ddr_poison_setup()
979 bank |= (((hif_addr >> priv->bank_shift[index]) & in ddr_poison_setup()
986 if (priv->bankgrp_shift[index]) in ddr_poison_setup()
987 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) in ddr_poison_setup()
993 if (priv->rank_shift[0]) in ddr_poison_setup()
994 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); in ddr_poison_setup()
998 writel(regval, priv->baseaddr + ECC_POISON0_OFST); in ddr_poison_setup()
1003 writel(regval, priv->baseaddr + ECC_POISON1_OFST); in ddr_poison_setup()
1011 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_show()
1015 readl(priv->baseaddr + ECC_POISON0_OFST), in inject_data_error_show()
1016 readl(priv->baseaddr + ECC_POISON1_OFST), in inject_data_error_show()
1017 priv->poison_addr); in inject_data_error_show()
1025 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_store()
1027 if (kstrtoul(data, 0, &priv->poison_addr)) in inject_data_error_store()
1028 return -EINVAL; in inject_data_error_store()
1040 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_show()
1043 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) in inject_data_poison_show()
1052 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_store()
1054 writel(0, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1056 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1058 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1059 writel(1, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1071 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); in edac_create_sysfs_attributes()
1074 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); in edac_create_sysfs_attributes()
1082 device_remove_file(&mci->dev, &dev_attr_inject_data_error); in edac_remove_sysfs_attributes()
1083 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); in edac_remove_sysfs_attributes()
1091 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; in setup_row_address_map()
1092 priv->row_shift[1] = ((addrmap[5] >> 8) & in setup_row_address_map()
1098 priv->row_shift[index] = addrmap_row_b2_10 + in setup_row_address_map()
1102 priv->row_shift[2] = (addrmap[9] & in setup_row_address_map()
1104 priv->row_shift[3] = ((addrmap[9] >> 8) & in setup_row_address_map()
1106 priv->row_shift[4] = ((addrmap[9] >> 16) & in setup_row_address_map()
1108 priv->row_shift[5] = ((addrmap[9] >> 24) & in setup_row_address_map()
1110 priv->row_shift[6] = (addrmap[10] & in setup_row_address_map()
1112 priv->row_shift[7] = ((addrmap[10] >> 8) & in setup_row_address_map()
1114 priv->row_shift[8] = ((addrmap[10] >> 16) & in setup_row_address_map()
1116 priv->row_shift[9] = ((addrmap[10] >> 24) & in setup_row_address_map()
1118 priv->row_shift[10] = (addrmap[11] & in setup_row_address_map()
1122 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1125 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1128 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1131 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1134 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1137 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1140 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1150 memtype = readl(priv->baseaddr + CTRL_OFST); in setup_column_address_map()
1153 priv->col_shift[0] = 0; in setup_column_address_map()
1154 priv->col_shift[1] = 1; in setup_column_address_map()
1155 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; in setup_column_address_map()
1156 priv->col_shift[3] = ((addrmap[2] >> 8) & in setup_column_address_map()
1158 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1161 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1164 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == in setup_column_address_map()
1167 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1170 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1173 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1178 priv->col_shift[10] = ((addrmap[4] & in setup_column_address_map()
1182 priv->col_shift[11] = (((addrmap[4] >> 8) & in setup_column_address_map()
1187 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1191 priv->col_shift[13] = (((addrmap[4] >> 8) & in setup_column_address_map()
1198 priv->col_shift[10] = (((addrmap[3] >> 24) & in setup_column_address_map()
1202 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1207 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1211 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1218 priv->col_shift[10] = (((addrmap[3] >> 16) & in setup_column_address_map()
1222 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1226 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1231 priv->col_shift[11] = (((addrmap[3] >> 16) & in setup_column_address_map()
1235 priv->col_shift[13] = (((addrmap[3] >> 24) & in setup_column_address_map()
1243 for (index = 9; index > width; index--) { in setup_column_address_map()
1244 priv->col_shift[index] = priv->col_shift[index - width]; in setup_column_address_map()
1245 priv->col_shift[index - width] = 0; in setup_column_address_map()
1253 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; in setup_bank_address_map()
1254 priv->bank_shift[1] = ((addrmap[1] >> 8) & in setup_bank_address_map()
1256 priv->bank_shift[2] = (((addrmap[1] >> 16) & in setup_bank_address_map()
1265 priv->bankgrp_shift[0] = (addrmap[8] & in setup_bg_address_map()
1267 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == in setup_bg_address_map()
1275 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == in setup_rank_address_map()
1281 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1297 addrmap[index] = readl(priv->baseaddr + addrmap_offset); in setup_address_map()
1313 * mc_probe - Check controller and bind driver.
1332 baseaddr = devm_ioremap_resource(&pdev->dev, res); in mc_probe()
1336 p_data = of_device_get_match_data(&pdev->dev); in mc_probe()
1338 return -ENODEV; in mc_probe()
1340 if (!p_data->get_ecc_state(baseaddr)) { in mc_probe()
1342 return -ENXIO; in mc_probe()
1357 return -ENOMEM; in mc_probe()
1360 priv = mci->pvt_info; in mc_probe()
1361 priv->baseaddr = baseaddr; in mc_probe()
1362 priv->p_data = p_data; in mc_probe()
1366 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_probe()
1380 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { in mc_probe()
1389 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_probe()
1397 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) in mc_probe()
1409 * mc_remove - Unbind driver from controller.
1417 struct synps_edac_priv *priv = mci->pvt_info; in mc_remove()
1419 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_remove()
1423 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) in mc_remove()
1427 edac_mc_del_mc(&pdev->dev); in mc_remove()
1435 .name = "synopsys-edac",