Lines Matching +full:0 +full:- +full:19
1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define PPC_REG_VAL(bit, val) ((val) << ((PPC_REG_BITS - 1) - (bit)))
21 #define PPC_REG_DECODE(bit, val) ((val) >> ((PPC_REG_BITS - 1) - (bit)))
27 #define SDRAM_BESR 0x00 /* Error status (read/clear) */
28 #define SDRAM_BESRT 0x01 /* Error statuss (test/set) */
29 #define SDRAM_BEARL 0x02 /* Error address low */
30 #define SDRAM_BEARH 0x03 /* Error address high */
31 #define SDRAM_WMIRQ 0x06 /* Write master (read/clear) */
32 #define SDRAM_WMIRQT 0x07 /* Write master (test/set) */
33 #define SDRAM_MCOPT1 0x20 /* Controller options 1 */
34 #define SDRAM_MBXCF_BASE 0x40 /* Bank n configuration base */
36 #define SDRAM_MB0CF SDRAM_MBXCF(0)
40 #define SDRAM_ECCCR 0x98 /* ECC error status */
46 #define SDRAM_PLB_M0ID_FIRST 0
57 #define SDRAM_PLB_M0ID_COUNT (SDRAM_PLB_M0ID_LAST - \
63 #define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
64 #define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
75 #define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
76 #define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0)
79 #define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
85 #define SDRAM_WMIRQ_MASK PPC_REG_VAL(8, 0x1FF)
101 #define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */
102 #define SDRAM_MCOPT1_MCHK_NON PPC_REG_VAL(3, 0x0) /* No ECC gen */
103 #define SDRAM_MCOPT1_MCHK_GEN PPC_REG_VAL(3, 0x2) /* ECC gen */
104 #define SDRAM_MCOPT1_MCHK_CHK PPC_REG_VAL(3, 0x1) /* ECC gen and chk */
105 #define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */
106 #define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
107 #define SDRAM_MCOPT1_RDEN_MASK PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM mask */
108 #define SDRAM_MCOPT1_RDEN PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM enbl */
109 #define SDRAM_MCOPT1_WDTH_MASK PPC_REG_VAL(7, 0x1) /* Width mask */
110 #define SDRAM_MCOPT1_WDTH_32 PPC_REG_VAL(7, 0x0) /* 32 bits */
111 #define SDRAM_MCOPT1_WDTH_16 PPC_REG_VAL(7, 0x1) /* 16 bits */
112 #define SDRAM_MCOPT1_DDR_TYPE_MASK PPC_REG_VAL(11, 0x1) /* DDR type mask */
113 #define SDRAM_MCOPT1_DDR1_TYPE PPC_REG_VAL(11, 0x0) /* DDR1 type */
114 #define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */
117 * Memory Bank 0 - n Configuration Register
119 #define SDRAM_MBCF_BA_MASK PPC_REG_VAL(12, 0x1FFF)
120 #define SDRAM_MBCF_SZ_MASK PPC_REG_VAL(19, 0xF)
121 #define SDRAM_MBCF_SZ_DECODE(mbxcf) PPC_REG_DECODE(19, mbxcf)
122 #define SDRAM_MBCF_SZ_4MB PPC_REG_VAL(19, 0x0)
123 #define SDRAM_MBCF_SZ_8MB PPC_REG_VAL(19, 0x1)
124 #define SDRAM_MBCF_SZ_16MB PPC_REG_VAL(19, 0x2)
125 #define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3)
126 #define SDRAM_MBCF_SZ_64MB PPC_REG_VAL(19, 0x4)
127 #define SDRAM_MBCF_SZ_128MB PPC_REG_VAL(19, 0x5)
128 #define SDRAM_MBCF_SZ_256MB PPC_REG_VAL(19, 0x6)
129 #define SDRAM_MBCF_SZ_512MB PPC_REG_VAL(19, 0x7)
130 #define SDRAM_MBCF_SZ_1GB PPC_REG_VAL(19, 0x8)
131 #define SDRAM_MBCF_SZ_2GB PPC_REG_VAL(19, 0x9)
132 #define SDRAM_MBCF_SZ_4GB PPC_REG_VAL(19, 0xA)
133 #define SDRAM_MBCF_SZ_8GB PPC_REG_VAL(19, 0xB)
134 #define SDRAM_MBCF_AM_MASK PPC_REG_VAL(23, 0xF)
135 #define SDRAM_MBCF_AM_MODE0 PPC_REG_VAL(23, 0x0)
136 #define SDRAM_MBCF_AM_MODE1 PPC_REG_VAL(23, 0x1)
137 #define SDRAM_MBCF_AM_MODE2 PPC_REG_VAL(23, 0x2)
138 #define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3)
139 #define SDRAM_MBCF_AM_MODE4 PPC_REG_VAL(23, 0x4)
140 #define SDRAM_MBCF_AM_MODE5 PPC_REG_VAL(23, 0x5)
141 #define SDRAM_MBCF_AM_MODE6 PPC_REG_VAL(23, 0x6)
142 #define SDRAM_MBCF_AM_MODE7 PPC_REG_VAL(23, 0x7)
143 #define SDRAM_MBCF_AM_MODE8 PPC_REG_VAL(23, 0x8)
144 #define SDRAM_MBCF_AM_MODE9 PPC_REG_VAL(23, 0x9)
145 #define SDRAM_MBCF_BE_MASK PPC_REG_VAL(31, 0x1)
146 #define SDRAM_MBCF_BE_DISABLE PPC_REG_VAL(31, 0x0)
147 #define SDRAM_MBCF_BE_ENABLE PPC_REG_VAL(31, 0x1)
152 #define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
153 #define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
154 #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
155 #define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
156 #define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
162 #define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
163 #define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)