Lines Matching +full:0 +full:- +full:5
1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #define b_cr_touud_lo_pci_port 0x4c
18 #define b_cr_touud_lo_pci_offset 0xa8
19 #define b_cr_touud_lo_pci_r_opcode 0x04
26 #define b_cr_touud_hi_pci_port 0x4c
27 #define b_cr_touud_hi_pci_offset 0xac
28 #define b_cr_touud_hi_pci_r_opcode 0x04
36 #define b_cr_tolud_pci_port 0x4c
37 #define b_cr_tolud_pci_offset 0xbc
38 #define b_cr_tolud_pci_r_opcode 0x04
71 #define b_cr_slice_channel_hash_port 0x4c
72 #define b_cr_slice_channel_hash_offset 0x4c58
73 #define b_cr_slice_channel_hash_r_opcode 0x06
83 #define b_cr_mot_out_base_mchbar_port 0x4c
84 #define b_cr_mot_out_base_mchbar_offset 0x6af0
85 #define b_cr_mot_out_base_mchbar_r_opcode 0x00
95 #define b_cr_mot_out_mask_mchbar_port 0x4c
96 #define b_cr_mot_out_mask_mchbar_offset 0x6af4
97 #define b_cr_mot_out_mask_mchbar_r_opcode 0x00
108 #define b_cr_asym_mem_region0_mchbar_port 0x4c
109 #define b_cr_asym_mem_region0_mchbar_offset 0x6e40
110 #define b_cr_asym_mem_region0_mchbar_r_opcode 0x00
121 #define b_cr_asym_mem_region1_mchbar_port 0x4c
122 #define b_cr_asym_mem_region1_mchbar_offset 0x6e44
123 #define b_cr_asym_mem_region1_mchbar_r_opcode 0x00
145 #define b_cr_asym_2way_mem_region_mchbar_port 0x4c
146 #define b_cr_asym_2way_mem_region_mchbar_offset 0x6e50
147 #define b_cr_asym_2way_mem_region_mchbar_r_opcode 0x00
149 /* Apollo Lake d-unit */
158 u32 rsvd13_9 : 5;
170 #define d_cr_drp0_offset 0x1400
171 #define d_cr_drp0_r_opcode 0x00
173 /* Denverton d-unit */
189 #define d_cr_dsch_port 0x16
190 #define d_cr_dsch_offset 0x0
191 #define d_cr_dsch_r_opcode 0x0
198 #define d_cr_ecc_ctrl_offset 0x180
199 #define d_cr_ecc_ctrl_r_opcode 0x0
215 #define d_cr_drp_offset 0x158
216 #define d_cr_drp_r_opcode 0x0
219 u32 ba0 : 5;
220 u32 ba1 : 5;
221 u32 bg0 : 5; /* if ddr3, ba2 = bg0 */
222 u32 bg1 : 5; /* if ddr3, ba3 = bg1 */
223 u32 rs0 : 5;
224 u32 rs1 : 5;
228 #define d_cr_dmap_offset 0x174
229 #define d_cr_dmap_r_opcode 0x0
237 #define d_cr_dmap1_offset 0xb4
238 #define d_cr_dmap1_r_opcode 0x0
241 u32 row0 : 5;
242 u32 row1 : 5;
243 u32 row2 : 5;
244 u32 row3 : 5;
245 u32 row4 : 5;
246 u32 row5 : 5;
250 #define d_cr_dmap2_offset 0x148
251 #define d_cr_dmap2_r_opcode 0x0
254 u32 row6 : 5;
255 u32 row7 : 5;
256 u32 row8 : 5;
257 u32 row9 : 5;
258 u32 row10 : 5;
259 u32 row11 : 5;
263 #define d_cr_dmap3_offset 0x14c
264 #define d_cr_dmap3_r_opcode 0x0
267 u32 row12 : 5;
268 u32 row13 : 5;
269 u32 row14 : 5;
270 u32 row15 : 5;
271 u32 row16 : 5;
272 u32 row17 : 5;
276 #define d_cr_dmap4_offset 0x150
277 #define d_cr_dmap4_r_opcode 0x0
290 #define d_cr_dmap5_offset 0x154
291 #define d_cr_dmap5_r_opcode 0x0