Lines Matching +full:ch +full:- +full:func
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
7 * and Westmere-EP.
9 * Copyright (c) 2009-2010 by:
23 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
51 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
92 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
132 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) argument
133 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) argument
187 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
190 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
230 int func; member
281 .func = (function), \
310 /* Generic Non-core registers */
369 /* Generic Non-core registers */
396 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) argument
397 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
400 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
401 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) argument
411 static const int ranks[] = { 1, 2, 4, -EINVAL }; in numrank()
418 static const int banks[] = { 4, 8, 16, -EINVAL }; in numbank()
427 1 << 16, -EINVAL, -EINVAL, -EINVAL, in numrow()
436 1 << 10, 1 << 11, 1 << 12, -EINVAL, in numcol()
446 if (i7core_dev->socket == socket) in get_i7core_dev()
462 i7core_dev->pdev = kcalloc(table->n_devs, sizeof(*i7core_dev->pdev), in alloc_i7core_dev()
464 if (!i7core_dev->pdev) { in alloc_i7core_dev()
469 i7core_dev->socket = socket; in alloc_i7core_dev()
470 i7core_dev->n_devs = table->n_devs; in alloc_i7core_dev()
471 list_add_tail(&i7core_dev->list, &i7core_edac_list); in alloc_i7core_dev()
478 list_del(&i7core_dev->list); in free_i7core_dev()
479 kfree(i7core_dev->pdev); in free_i7core_dev()
489 struct i7core_pvt *pvt = mci->pvt_info; in get_dimm_config()
497 pdev = pvt->pci_mcr[0]; in get_dimm_config()
499 return -ENODEV; in get_dimm_config()
502 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); in get_dimm_config()
503 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); in get_dimm_config()
504 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); in get_dimm_config()
505 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); in get_dimm_config()
508 pvt->i7core_dev->socket, pvt->info.mc_control, in get_dimm_config()
509 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map); in get_dimm_config()
523 edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n", in get_dimm_config()
524 numdimms(pvt->info.max_dod), in get_dimm_config()
525 numrank(pvt->info.max_dod >> 2), in get_dimm_config()
526 numbank(pvt->info.max_dod >> 4), in get_dimm_config()
527 numrow(pvt->info.max_dod >> 6), in get_dimm_config()
528 numcol(pvt->info.max_dod >> 9)); in get_dimm_config()
533 if (!pvt->pci_ch[i][0]) in get_dimm_config()
545 /* Devices 4-6 function 0 */ in get_dimm_config()
546 pci_read_config_dword(pvt->pci_ch[i][0], in get_dimm_config()
551 pvt->channel[i].is_3dimms_present = true; in get_dimm_config()
554 pvt->channel[i].is_single_4rank = true; in get_dimm_config()
557 pvt->channel[i].has_4rank = true; in get_dimm_config()
564 /* Devices 4-6 function 1 */ in get_dimm_config()
565 pci_read_config_dword(pvt->pci_ch[i][1], in get_dimm_config()
567 pci_read_config_dword(pvt->pci_ch[i][1], in get_dimm_config()
569 pci_read_config_dword(pvt->pci_ch[i][1], in get_dimm_config()
572 edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n", in get_dimm_config()
574 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), in get_dimm_config()
576 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "", in get_dimm_config()
577 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "", in get_dimm_config()
578 pvt->channel[i].has_4rank ? "HAS_4R " : "", in get_dimm_config()
595 size = (rows * cols * banks * ranks) >> (20 - 3); in get_dimm_config()
604 dimm->nr_pages = npages; in get_dimm_config()
608 dimm->dtype = DEV_X4; in get_dimm_config()
611 dimm->dtype = DEV_X8; in get_dimm_config()
614 dimm->dtype = DEV_X16; in get_dimm_config()
617 dimm->dtype = DEV_UNKNOWN; in get_dimm_config()
620 snprintf(dimm->label, sizeof(dimm->label), in get_dimm_config()
622 pvt->i7core_dev->socket, i, j); in get_dimm_config()
623 dimm->grain = 8; in get_dimm_config()
624 dimm->edac_mode = mode; in get_dimm_config()
625 dimm->mtype = mtype; in get_dimm_config()
641 (value[j] & ((1 << 24) - 1))); in get_dimm_config()
662 struct i7core_pvt *pvt = mci->pvt_info; in disable_inject()
664 pvt->inject.enable = 0; in disable_inject()
666 if (!pvt->pci_ch[pvt->inject.channel][0]) in disable_inject()
667 return -ENODEV; in disable_inject()
669 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], in disable_inject()
679 * bit 0 - refers to the lower 32-byte half cacheline
680 * bit 1 - refers to the upper 32-byte half cacheline
687 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_section_store()
691 if (pvt->inject.enable) in i7core_inject_section_store()
696 return -EIO; in i7core_inject_section_store()
698 pvt->inject.section = (u32) value; in i7core_inject_section_store()
707 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_section_show()
708 return sprintf(data, "0x%08x\n", pvt->inject.section); in i7core_inject_section_show()
715 * bit 0 - repeat enable - Enable error repetition
716 * bit 1 - inject ECC error
717 * bit 2 - inject parity error
724 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_type_store()
728 if (pvt->inject.enable) in i7core_inject_type_store()
733 return -EIO; in i7core_inject_type_store()
735 pvt->inject.type = (u32) value; in i7core_inject_type_store()
744 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_type_show()
746 return sprintf(data, "0x%08x\n", pvt->inject.type); in i7core_inject_type_show()
755 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
764 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_eccmask_store()
768 if (pvt->inject.enable) in i7core_inject_eccmask_store()
773 return -EIO; in i7core_inject_eccmask_store()
775 pvt->inject.eccmask = (u32) value; in i7core_inject_eccmask_store()
784 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_eccmask_show()
786 return sprintf(data, "0x%08x\n", pvt->inject.eccmask); in i7core_inject_eccmask_show()
795 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
812 pvt = mci->pvt_info; \
814 if (pvt->inject.enable) \
818 value = -1; \
822 return -EIO; \
825 pvt->inject.param = value; \
838 pvt = mci->pvt_info; \
840 if (pvt->inject.param < 0) \
843 return sprintf(data, "%d\n", pvt->inject.param);\
871 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), in write_and_test()
886 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), in write_and_test()
889 return -EINVAL; in write_and_test()
898 * A -1 value for any of the mask items will make the MCU to ignore
915 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_enable_store()
921 if (!pvt->pci_ch[pvt->inject.channel][0]) in i7core_inject_enable_store()
929 pvt->inject.enable = 1; in i7core_inject_enable_store()
935 /* Sets pvt->inject.dimm mask */ in i7core_inject_enable_store()
936 if (pvt->inject.dimm < 0) in i7core_inject_enable_store()
939 if (pvt->channel[pvt->inject.channel].dimms > 2) in i7core_inject_enable_store()
940 mask |= (pvt->inject.dimm & 0x3LL) << 35; in i7core_inject_enable_store()
942 mask |= (pvt->inject.dimm & 0x1LL) << 36; in i7core_inject_enable_store()
945 /* Sets pvt->inject.rank mask */ in i7core_inject_enable_store()
946 if (pvt->inject.rank < 0) in i7core_inject_enable_store()
949 if (pvt->channel[pvt->inject.channel].dimms > 2) in i7core_inject_enable_store()
950 mask |= (pvt->inject.rank & 0x1LL) << 34; in i7core_inject_enable_store()
952 mask |= (pvt->inject.rank & 0x3LL) << 34; in i7core_inject_enable_store()
955 /* Sets pvt->inject.bank mask */ in i7core_inject_enable_store()
956 if (pvt->inject.bank < 0) in i7core_inject_enable_store()
959 mask |= (pvt->inject.bank & 0x15LL) << 30; in i7core_inject_enable_store()
961 /* Sets pvt->inject.page mask */ in i7core_inject_enable_store()
962 if (pvt->inject.page < 0) in i7core_inject_enable_store()
965 mask |= (pvt->inject.page & 0xffff) << 14; in i7core_inject_enable_store()
967 /* Sets pvt->inject.column mask */ in i7core_inject_enable_store()
968 if (pvt->inject.col < 0) in i7core_inject_enable_store()
971 mask |= (pvt->inject.col & 0x3fff); in i7core_inject_enable_store()
975 * bits 1-2: MASK_HALF_CACHELINE in i7core_inject_enable_store()
980 injectmask = (pvt->inject.type & 1) | in i7core_inject_enable_store()
981 (pvt->inject.section & 0x3) << 1 | in i7core_inject_enable_store()
982 (pvt->inject.type & 0x6) << (3 - 1); in i7core_inject_enable_store()
984 /* Unlock writes to registers - this register is write only */ in i7core_inject_enable_store()
985 pci_write_config_dword(pvt->pci_noncore, in i7core_inject_enable_store()
988 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
990 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
993 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
994 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); in i7core_inject_enable_store()
996 write_and_test(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_store()
1004 pci_write_config_dword(pvt->pci_noncore, in i7core_inject_enable_store()
1008 mask, pvt->inject.eccmask, injectmask); in i7core_inject_enable_store()
1019 struct i7core_pvt *pvt = mci->pvt_info; in i7core_inject_enable_show()
1022 if (!pvt->pci_ch[pvt->inject.channel][0]) in i7core_inject_enable_show()
1025 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], in i7core_inject_enable_show()
1031 pvt->inject.enable = 1; in i7core_inject_enable_show()
1033 return sprintf(data, "%d\n", pvt->inject.enable); in i7core_inject_enable_show()
1043 struct i7core_pvt *pvt = mci->pvt_info; \
1046 if (!pvt->ce_count_available || (pvt->is_registered)) \
1049 pvt->udimm_ce_count[param]); \
1159 struct i7core_pvt *pvt = mci->pvt_info; in i7core_create_sysfs_devices()
1162 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL); in i7core_create_sysfs_devices()
1163 if (!pvt->addrmatch_dev) in i7core_create_sysfs_devices()
1164 return -ENOMEM; in i7core_create_sysfs_devices()
1166 pvt->addrmatch_dev->type = &addrmatch_type; in i7core_create_sysfs_devices()
1167 pvt->addrmatch_dev->bus = mci->dev.bus; in i7core_create_sysfs_devices()
1168 device_initialize(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1169 pvt->addrmatch_dev->parent = &mci->dev; in i7core_create_sysfs_devices()
1170 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch"); in i7core_create_sysfs_devices()
1171 dev_set_drvdata(pvt->addrmatch_dev, mci); in i7core_create_sysfs_devices()
1173 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev)); in i7core_create_sysfs_devices()
1175 rc = device_add(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1179 if (!pvt->is_registered) { in i7core_create_sysfs_devices()
1180 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev), in i7core_create_sysfs_devices()
1182 if (!pvt->chancounts_dev) { in i7core_create_sysfs_devices()
1183 rc = -ENOMEM; in i7core_create_sysfs_devices()
1187 pvt->chancounts_dev->type = &all_channel_counts_type; in i7core_create_sysfs_devices()
1188 pvt->chancounts_dev->bus = mci->dev.bus; in i7core_create_sysfs_devices()
1189 device_initialize(pvt->chancounts_dev); in i7core_create_sysfs_devices()
1190 pvt->chancounts_dev->parent = &mci->dev; in i7core_create_sysfs_devices()
1191 dev_set_name(pvt->chancounts_dev, "all_channel_counts"); in i7core_create_sysfs_devices()
1192 dev_set_drvdata(pvt->chancounts_dev, mci); in i7core_create_sysfs_devices()
1194 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev)); in i7core_create_sysfs_devices()
1196 rc = device_add(pvt->chancounts_dev); in i7core_create_sysfs_devices()
1203 put_device(pvt->chancounts_dev); in i7core_create_sysfs_devices()
1205 device_del(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1207 put_device(pvt->addrmatch_dev); in i7core_create_sysfs_devices()
1214 struct i7core_pvt *pvt = mci->pvt_info; in i7core_delete_sysfs_devices()
1218 if (!pvt->is_registered) { in i7core_delete_sysfs_devices()
1219 device_del(pvt->chancounts_dev); in i7core_delete_sysfs_devices()
1220 put_device(pvt->chancounts_dev); in i7core_delete_sysfs_devices()
1222 device_del(pvt->addrmatch_dev); in i7core_delete_sysfs_devices()
1223 put_device(pvt->addrmatch_dev); in i7core_delete_sysfs_devices()
1239 for (i = 0; i < i7core_dev->n_devs; i++) { in i7core_put_devices()
1240 struct pci_dev *pdev = i7core_dev->pdev[i]; in i7core_put_devices()
1244 pdev->bus->number, in i7core_put_devices()
1245 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); in i7core_put_devices()
1266 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses in i7core_xeon_pci_fixup()
1270 while (table && table->descr) { in i7core_xeon_pci_fixup()
1271 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL); in i7core_xeon_pci_fixup()
1274 pcibios_scan_specific_bus(255-i); in i7core_xeon_pci_fixup()
1287 bus = b->number; in i7core_pci_lastbus()
1302 * Need to 'get' device 16 func 1 and func 2
1310 const struct pci_id_descr *dev_descr = &table->descr[devno]; in i7core_get_onedevice()
1317 dev_descr->dev_id, *prev); in i7core_get_onedevice()
1320 * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs in i7core_get_onedevice()
1324 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) { in i7core_get_onedevice()
1330 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && in i7core_get_onedevice()
1344 if (dev_descr->optional) in i7core_get_onedevice()
1348 return -ENODEV; in i7core_get_onedevice()
1352 dev_descr->dev, dev_descr->func, in i7core_get_onedevice()
1353 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in i7core_get_onedevice()
1356 return -ENODEV; in i7core_get_onedevice()
1358 bus = pdev->bus->number; in i7core_get_onedevice()
1360 socket = last_bus - bus; in i7core_get_onedevice()
1367 return -ENOMEM; in i7core_get_onedevice()
1371 if (i7core_dev->pdev[devno]) { in i7core_get_onedevice()
1375 bus, dev_descr->dev, dev_descr->func, in i7core_get_onedevice()
1376 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in i7core_get_onedevice()
1378 return -ENODEV; in i7core_get_onedevice()
1381 i7core_dev->pdev[devno] = pdev; in i7core_get_onedevice()
1384 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || in i7core_get_onedevice()
1385 PCI_FUNC(pdev->devfn) != dev_descr->func)) { in i7core_get_onedevice()
1389 PCI_VENDOR_ID_INTEL, dev_descr->dev_id, in i7core_get_onedevice()
1390 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in i7core_get_onedevice()
1391 bus, dev_descr->dev, dev_descr->func); in i7core_get_onedevice()
1392 return -ENODEV; in i7core_get_onedevice()
1400 bus, dev_descr->dev, dev_descr->func, in i7core_get_onedevice()
1401 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in i7core_get_onedevice()
1402 return -ENODEV; in i7core_get_onedevice()
1406 socket, bus, dev_descr->dev, in i7core_get_onedevice()
1407 dev_descr->func, in i7core_get_onedevice()
1408 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in i7core_get_onedevice()
1430 while (table && table->descr) { in i7core_get_all_devices()
1431 for (i = 0; i < table->n_devs; i++) { in i7core_get_all_devices()
1438 i = table->n_devs; in i7core_get_all_devices()
1442 return -ENODEV; in i7core_get_all_devices()
1455 struct i7core_pvt *pvt = mci->pvt_info; in mci_bind_devs()
1457 int i, func, slot; in mci_bind_devs() local
1460 pvt->is_registered = false; in mci_bind_devs()
1461 pvt->enable_scrub = false; in mci_bind_devs()
1462 for (i = 0; i < i7core_dev->n_devs; i++) { in mci_bind_devs()
1463 pdev = i7core_dev->pdev[i]; in mci_bind_devs()
1467 func = PCI_FUNC(pdev->devfn); in mci_bind_devs()
1468 slot = PCI_SLOT(pdev->devfn); in mci_bind_devs()
1470 if (unlikely(func > MAX_MCR_FUNC)) in mci_bind_devs()
1472 pvt->pci_mcr[func] = pdev; in mci_bind_devs()
1474 if (unlikely(func > MAX_CHAN_FUNC)) in mci_bind_devs()
1476 pvt->pci_ch[slot - 4][func] = pdev; in mci_bind_devs()
1477 } else if (!slot && !func) { in mci_bind_devs()
1478 pvt->pci_noncore = pdev; in mci_bind_devs()
1481 switch (pdev->device) { in mci_bind_devs()
1484 pvt->enable_scrub = false; in mci_bind_devs()
1487 family = "i7-800/i5-700"; in mci_bind_devs()
1488 pvt->enable_scrub = false; in mci_bind_devs()
1492 pvt->enable_scrub = false; in mci_bind_devs()
1496 pvt->enable_scrub = true; in mci_bind_devs()
1499 family = "Xeon 56xx / i7-900"; in mci_bind_devs()
1500 pvt->enable_scrub = true; in mci_bind_devs()
1504 pvt->enable_scrub = false; in mci_bind_devs()
1511 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in mci_bind_devs()
1512 pdev, i7core_dev->socket); in mci_bind_devs()
1514 if (PCI_SLOT(pdev->devfn) == 3 && in mci_bind_devs()
1515 PCI_FUNC(pdev->devfn) == 2) in mci_bind_devs()
1516 pvt->is_registered = true; in mci_bind_devs()
1524 slot, func); in mci_bind_devs()
1525 return -EINVAL; in mci_bind_devs()
1538 struct i7core_pvt *pvt = mci->pvt_info; in i7core_rdimm_update_ce_count()
1541 if (pvt->ce_count_available) { in i7core_rdimm_update_ce_count()
1544 add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; in i7core_rdimm_update_ce_count()
1545 add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; in i7core_rdimm_update_ce_count()
1546 add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; in i7core_rdimm_update_ce_count()
1550 pvt->rdimm_ce_count[chan][2] += add2; in i7core_rdimm_update_ce_count()
1554 pvt->rdimm_ce_count[chan][1] += add1; in i7core_rdimm_update_ce_count()
1558 pvt->rdimm_ce_count[chan][0] += add0; in i7core_rdimm_update_ce_count()
1560 pvt->ce_count_available = 1; in i7core_rdimm_update_ce_count()
1563 pvt->rdimm_last_ce_count[chan][2] = new2; in i7core_rdimm_update_ce_count()
1564 pvt->rdimm_last_ce_count[chan][1] = new1; in i7core_rdimm_update_ce_count()
1565 pvt->rdimm_last_ce_count[chan][0] = new0; in i7core_rdimm_update_ce_count()
1571 chan, 0, -1, "error", ""); in i7core_rdimm_update_ce_count()
1575 chan, 1, -1, "error", ""); in i7core_rdimm_update_ce_count()
1579 chan, 2, -1, "error", ""); in i7core_rdimm_update_ce_count()
1584 struct i7core_pvt *pvt = mci->pvt_info; in i7core_rdimm_check_mc_ecc_err()
1589 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, in i7core_rdimm_check_mc_ecc_err()
1591 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, in i7core_rdimm_check_mc_ecc_err()
1593 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, in i7core_rdimm_check_mc_ecc_err()
1595 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, in i7core_rdimm_check_mc_ecc_err()
1597 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, in i7core_rdimm_check_mc_ecc_err()
1599 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, in i7core_rdimm_check_mc_ecc_err()
1605 if (pvt->channel[i].dimms > 2) { in i7core_rdimm_check_mc_ecc_err()
1625 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1629 struct i7core_pvt *pvt = mci->pvt_info; in i7core_udimm_check_mc_ecc_err()
1633 if (!pvt->pci_mcr[4]) { in i7core_udimm_check_mc_ecc_err()
1639 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); in i7core_udimm_check_mc_ecc_err()
1640 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); in i7core_udimm_check_mc_ecc_err()
1648 if (pvt->ce_count_available) { in i7core_udimm_check_mc_ecc_err()
1652 add2 = new2 - pvt->udimm_last_ce_count[2]; in i7core_udimm_check_mc_ecc_err()
1653 add1 = new1 - pvt->udimm_last_ce_count[1]; in i7core_udimm_check_mc_ecc_err()
1654 add0 = new0 - pvt->udimm_last_ce_count[0]; in i7core_udimm_check_mc_ecc_err()
1658 pvt->udimm_ce_count[2] += add2; in i7core_udimm_check_mc_ecc_err()
1662 pvt->udimm_ce_count[1] += add1; in i7core_udimm_check_mc_ecc_err()
1666 pvt->udimm_ce_count[0] += add0; in i7core_udimm_check_mc_ecc_err()
1673 pvt->ce_count_available = 1; in i7core_udimm_check_mc_ecc_err()
1676 pvt->udimm_last_ce_count[2] = new2; in i7core_udimm_check_mc_ecc_err()
1677 pvt->udimm_last_ce_count[1] = new1; in i7core_udimm_check_mc_ecc_err()
1678 pvt->udimm_last_ce_count[0] = new0; in i7core_udimm_check_mc_ecc_err()
1682 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1688 * m->status MSR_IA32_MC8_STATUS
1689 * m->addr MSR_IA32_MC8_ADDR
1690 * m->misc MSR_IA32_MC8_MISC
1697 struct i7core_pvt *pvt = mci->pvt_info; in i7core_mce_output_error()
1700 unsigned long error = m->status & 0x1ff0000l; in i7core_mce_output_error()
1701 bool uncorrected_error = m->mcgstatus & 1ll << 61; in i7core_mce_output_error()
1702 bool ripv = m->mcgstatus & 1; in i7core_mce_output_error()
1703 u32 optypenum = (m->status >> 4) & 0x07; in i7core_mce_output_error()
1704 u32 core_err_cnt = (m->status >> 38) & 0x7fff; in i7core_mce_output_error()
1705 u32 dimm = (m->misc >> 16) & 0x3; in i7core_mce_output_error()
1706 u32 channel = (m->misc >> 18) & 0x3; in i7core_mce_output_error()
1707 u32 syndrome = m->misc >> 32; in i7core_mce_output_error()
1778 if (uncorrected_error || !pvt->is_registered) in i7core_mce_output_error()
1780 m->addr >> PAGE_SHIFT, in i7core_mce_output_error()
1781 m->addr & ~PAGE_MASK, in i7core_mce_output_error()
1783 channel, dimm, -1, in i7core_mce_output_error()
1793 struct i7core_pvt *pvt = mci->pvt_info; in i7core_check_error()
1800 if (!pvt->is_registered) in i7core_check_error()
1817 i7_dev = get_i7core_dev(mce->socketid); in i7core_mce_check_error()
1818 if (!i7_dev || (mce->kflags & MCE_HANDLED_CEC)) in i7core_mce_check_error()
1821 mci = i7_dev->mci; in i7core_mce_check_error()
1827 if (((mce->status & 0xffff) >> 7) != 1) in i7core_mce_check_error()
1831 if (mce->bank != 8) in i7core_mce_check_error()
1837 mce->kflags |= MCE_HANDLED_EDAC; in i7core_mce_check_error()
1882 if (*dclk_freq == -1) in decode_dclk()
1885 if (dh->type == DMI_ENTRY_MEM_DEVICE) { in decode_dclk()
1889 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed - in decode_dclk()
1890 (unsigned long)&memdev_dmi_entry->type; in decode_dclk()
1892 (unsigned long)&memdev_dmi_entry->speed - in decode_dclk()
1893 (unsigned long)&memdev_dmi_entry->type; in decode_dclk()
1896 if (memdev_dmi_entry->size == 0) in decode_dclk()
1903 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) { in decode_dclk()
1905 memdev_dmi_entry->conf_mem_clk_speed; in decode_dclk()
1906 } else if (memdev_dmi_entry->length > speed_offset) { in decode_dclk()
1907 dmi_mem_clk_speed = memdev_dmi_entry->speed; in decode_dclk()
1909 *dclk_freq = -1; in decode_dclk()
1920 *dclk_freq = -1; in decode_dclk()
1928 *dclk_freq = -1; in decode_dclk()
1959 struct i7core_pvt *pvt = mci->pvt_info; in set_sdram_scrub_rate()
1965 pdev = pvt->pci_mcr[2]; in set_sdram_scrub_rate()
1967 return -ENODEV; in set_sdram_scrub_rate()
1984 const u32 freq_dclk_mhz = pvt->dclk_freq; in set_sdram_scrub_rate()
1995 return -EINVAL; in set_sdram_scrub_rate()
2021 struct i7core_pvt *pvt = mci->pvt_info; in get_sdram_scrub_rate()
2024 const u32 freq_dclk_mhz = pvt->dclk_freq; in get_sdram_scrub_rate()
2029 pdev = pvt->pci_mcr[2]; in get_sdram_scrub_rate()
2031 return -ENODEV; in get_sdram_scrub_rate()
2036 /* Mask highest 8-bits to 0 */ in get_sdram_scrub_rate()
2050 struct i7core_pvt *pvt = mci->pvt_info; in enable_sdram_scrub_setting()
2054 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); in enable_sdram_scrub_setting()
2056 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, in enable_sdram_scrub_setting()
2059 mci->set_sdram_scrub_rate = set_sdram_scrub_rate; in enable_sdram_scrub_setting()
2060 mci->get_sdram_scrub_rate = get_sdram_scrub_rate; in enable_sdram_scrub_setting()
2065 struct i7core_pvt *pvt = mci->pvt_info; in disable_sdram_scrub_setting()
2069 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); in disable_sdram_scrub_setting()
2071 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, in disable_sdram_scrub_setting()
2077 pvt->i7core_pci = edac_pci_create_generic_ctl( in i7core_pci_ctl_create()
2078 &pvt->i7core_dev->pdev[0]->dev, in i7core_pci_ctl_create()
2080 if (unlikely(!pvt->i7core_pci)) in i7core_pci_ctl_create()
2087 if (likely(pvt->i7core_pci)) in i7core_pci_ctl_release()
2088 edac_pci_release_generic_ctl(pvt->i7core_pci); in i7core_pci_ctl_release()
2092 pvt->i7core_dev->socket); in i7core_pci_ctl_release()
2093 pvt->i7core_pci = NULL; in i7core_pci_ctl_release()
2098 struct mem_ctl_info *mci = i7core_dev->mci; in i7core_unregister_mci()
2101 if (unlikely(!mci || !mci->pvt_info)) { in i7core_unregister_mci()
2102 edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev); in i7core_unregister_mci()
2108 pvt = mci->pvt_info; in i7core_unregister_mci()
2110 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); in i7core_unregister_mci()
2113 if (pvt->enable_scrub) in i7core_unregister_mci()
2121 edac_mc_del_mc(mci->pdev); in i7core_unregister_mci()
2123 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); in i7core_unregister_mci()
2124 kfree(mci->ctl_name); in i7core_unregister_mci()
2126 i7core_dev->mci = NULL; in i7core_unregister_mci()
2144 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers, in i7core_register_mci()
2147 return -ENOMEM; in i7core_register_mci()
2149 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); in i7core_register_mci()
2151 pvt = mci->pvt_info; in i7core_register_mci()
2155 pvt->i7core_dev = i7core_dev; in i7core_register_mci()
2156 i7core_dev->mci = mci; in i7core_register_mci()
2163 mci->mtype_cap = MEM_FLAG_DDR3; in i7core_register_mci()
2164 mci->edac_ctl_cap = EDAC_FLAG_NONE; in i7core_register_mci()
2165 mci->edac_cap = EDAC_FLAG_NONE; in i7core_register_mci()
2166 mci->mod_name = "i7core_edac.c"; in i7core_register_mci()
2168 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", i7core_dev->socket); in i7core_register_mci()
2169 if (!mci->ctl_name) { in i7core_register_mci()
2170 rc = -ENOMEM; in i7core_register_mci()
2174 mci->dev_name = pci_name(i7core_dev->pdev[0]); in i7core_register_mci()
2175 mci->ctl_page_to_phys = NULL; in i7core_register_mci()
2186 mci->pdev = &i7core_dev->pdev[0]->dev; in i7core_register_mci()
2189 if (pvt->enable_scrub) in i7core_register_mci()
2199 rc = -EINVAL; in i7core_register_mci()
2204 edac_mc_del_mc(mci->pdev); in i7core_register_mci()
2205 rc = -EINVAL; in i7core_register_mci()
2210 pvt->inject.channel = 0; in i7core_register_mci()
2211 pvt->inject.dimm = -1; in i7core_register_mci()
2212 pvt->inject.rank = -1; in i7core_register_mci()
2213 pvt->inject.bank = -1; in i7core_register_mci()
2214 pvt->inject.page = -1; in i7core_register_mci()
2215 pvt->inject.col = -1; in i7core_register_mci()
2221 pvt->dclk_freq = get_dclk_freq(); in i7core_register_mci()
2226 kfree(mci->ctl_name); in i7core_register_mci()
2230 i7core_dev->mci = NULL; in i7core_register_mci()
2255 return -ENODEV; in i7core_probe()
2271 * Nehalem-EX uses a different memory controller. However, as the in i7core_probe()
2272 * memory controller is not visible on some Nehalem/Nehalem-EP, we in i7core_probe()
2274 * are found on (some) Nehalem-EX. So, on those machines, the in i7core_probe()
2275 * probe routine needs to return -ENODEV, as the actual Memory in i7core_probe()
2279 rc = -ENODEV; in i7core_probe()
2331 probed--; in i7core_remove()
2395 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "