Lines Matching full:dram
25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
31 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
70 * 7:0 DRAM ECC Syndrome
79 * 9 LOCK to non-DRAM Memory Flag (LCKF)
82 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
83 * 0 Single-bit DRAM ECC Error Flag (DSERR)
95 * 9 SERR on LOCK to non-DRAM Memory
97 * 8 SERR on DRAM Refresh Timeout
100 * 1 SERR Multi-Bit DRAM ECC Error
110 #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
112 * 7:0 Channel 0 DRAM Rank Boundary Address
114 #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
116 * 7:0 Channel 1 DRAM Rank Boundary Address
119 #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
122 * 6:4 DRAM odd Rank Attribute
124 * 2:0 DRAM even Rank Attribute
135 #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
147 #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
156 * 1:0 DRAM Type (DT)
159 #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
381 * The dram rank boundary (DRB) reg values are boundary addresses in i3000_probe1()
382 * for each DRAM rank with a granularity of 32MB. DRB regs are in i3000_probe1()