Lines Matching +full:40 +full:x30

147  * F15 M30h D18F1x2[4C:40]
276 #define UMCCH_ADDR_MASK_SEC_DDR5	0x30
277 #define UMCCH_ADDR_CFG			0x30
326  * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
384 	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
443 	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;  in get_dram_base()
453 	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;  in get_dram_limit()
463 	if (pvt->fam == 0x15 && pvt->model >= 0x30)  in dct_sel_interleave_addr()
540 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in dram_intlv_en()
550 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in dhar_valid()
560 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in dct_sel_baseaddr()