Lines Matching +full:sifive +full:- +full:blocks

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
172 E3-1200 based DRAM controllers.
233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
248 system has non-volatile DIMMs you should also manually
260 system has non-volatile DIMMs you should also manually
271 micro-server but may appear on others in the future.
279 client SoC Integrated Memory Controller using In-Band ECC IP.
280 This In-Band ECC is first used on the Elkhart Lake SoC but
322 tristate "AMD8131 HyperTransport PCI-X Tunnel"
326 AMD8131 HyperTransport PCI-X Tunnel chip.
398 blocks (TAD, CBC, MCI).
426 bool "Altera On-Chip RAM ECC"
430 Altera On-Chip RAM Memory for Altera SoCs.
475 bool "Sifive platform EDAC driver"
478 Support for error detection and correction on the SiFive SoCs.
495 tristate "APM X-Gene SoC"
499 APM X-Gene family of SOCs.
538 tristate "ARM DMC-520 ECC"
542 SoCs with ARM DMC-520 DRAM controller.