Lines Matching +full:error +full:- +full:correction
13 tristate "EDAC (Error Detection And Correction) reporting"
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
82 Support for error detection and correction of DRAM ECC errors on
85 When EDAC_DEBUG is enabled, hardware error injection facilities
89 Error Injection into the ECC detection circuits. The amd64_edac
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
114 Support for error detection and correction on the AMD 76x
121 Support for error detection and correction on the Intel
128 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
143 Support for error detection and correction on the Intel
150 Support for error detection and correction on the Intel
157 Support for error detection and correction on the Intel
164 Support for error detection and correction on the Intel
171 Support for error detection and correction on the Intel
172 E3-1200 based DRAM controllers.
178 Support for error detection and correction on the Intel
185 Support for error detection and correction the Intel
192 Support for error detection and correction the Intel
201 Support for error detection and correction on the Intel
208 Support for error detection and correction on the Radisys
215 Support for error detection and correction the Intel
222 Support for error detection and correction the Intel
229 Support for error detection and correction the Intel
233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
236 Support for error detection and correction the Intel
246 Support for error detection and correction the Intel
248 system has non-volatile DIMMs you should also manually
258 Support for error detection and correction the Intel
260 system has non-volatile DIMMs you should also manually
268 Support for error detection and correction on the Intel
271 micro-server but may appear on others in the future.
278 Support for error detection and correction on the Intel
279 client SoC Integrated Memory Controller using In-Band ECC IP.
280 This In-Band ECC is first used on the Elkhart Lake SoC but
287 Support for error detection and correction on the Freescale
294 Support for error detection and correction on Freescale memory
301 Support for error detection and correction on PA Semi
308 Support for error detection and correction on the
322 tristate "AMD8131 HyperTransport PCI-X Tunnel"
325 Support for error detection and correction on the
326 AMD8131 HyperTransport PCI-X Tunnel chip.
334 Support for error detection and correction on the
343 Support for error detection and correction on the
352 Support for error detection and correction on the
359 Support for error detection and correction on the
366 Support for error detection and correction on the primary caches of
373 Support for error detection and correction on the
380 Support for error detection and correction on the
387 Support for error detection and correction on the
395 Support for error detection and correction on the
404 Support for error detection and correction on the
412 Support for error detection and correction on the
421 Support for error detection and correction on the
426 bool "Altera On-Chip RAM ECC"
429 Support for error detection and correction on the
430 Altera On-Chip RAM Memory for Altera SoCs.
436 Support for error detection and correction on the
443 Support for error detection and correction on the
450 Support for error detection and correction on the
457 Support for error detection and correction on the
464 Support for error detection and correction on the
471 Support for error detection and correction on the
478 Support for error detection and correction on the SiFive SoCs.
484 Support for error correction and detection on the Marvell Aramada XP
491 Support for error detection and correction on the Synopsys DDR
495 tristate "APM X-Gene SoC"
498 Support for error detection and correction on the
499 APM X-Gene family of SOCs.
505 Support for error detection and correction on the TI SoCs.
511 Support for error detection and correction on the
515 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
525 Support for error detection and correction on the Aspeed AST BMC SoC.
528 will expose error counters via the EDAC kernel framework.
534 Support for error detection and correction on the
538 tristate "ARM DMC-520 ECC"
541 Support for error detection and correction on the
542 SoCs with ARM DMC-520 DRAM controller.