Lines Matching +full:armada +full:- +full:xp +full:- +full:sdram +full:- +full:controller
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
93 When enabled, in each of the respective memory controller directories
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
104 tristate "Amazon's Annapurna Lab Memory Controller"
172 E3-1200 based DRAM controllers.
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
248 system has non-volatile DIMMs you should also manually
260 system has non-volatile DIMMs you should also manually
269 Pondicherry2 Integrated Memory Controller. This SoC IP is
271 micro-server but may appear on others in the future.
279 client SoC Integrated Memory Controller using In-Band ECC IP.
280 This In-Band ECC is first used on the Elkhart Lake SoC but
305 tristate "Cell Broadband Engine memory controller"
309 Cell Broadband Engine internal memory controller
313 tristate "PPC4xx IBM DDR2 Memory Controller"
317 with the IBM DDR2 memory controller found in various
322 tristate "AMD8131 HyperTransport PCI-X Tunnel"
326 AMD8131 HyperTransport PCI-X Tunnel chip.
340 tristate "IBM CPC925 Memory Controller (PPC970FX)"
344 IBM CPC925 Bridge and Memory Controller, which is
349 tristate "Highbank Memory Controller"
353 Calxeda Highbank memory controller.
360 Calxeda Highbank memory controller.
377 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
384 tristate "Cavium Octeon PCI Controller"
409 bool "Altera SDRAM ECC"
413 Altera SDRAM Memory for Altera SoCs. Note that the
414 preloader must initialize the SDRAM before loading
426 bool "Altera On-Chip RAM ECC"
430 Altera On-Chip RAM Memory for Altera SoCs.
481 bool "Marvell Armada XP DDR and L2 Cache ECC"
484 Support for error correction and detection on the Marvell Aramada XP
488 tristate "Synopsys DDR Memory Controller"
492 memory controller.
495 tristate "APM X-Gene SoC"
499 APM X-Gene family of SOCs.
502 tristate "Texas Instruments DDR3 ECC Controller"
508 tristate "QCOM EDAC Controller"
515 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
538 tristate "ARM DMC-520 ECC"
542 SoCs with ARM DMC-520 DRAM controller.