Lines Matching full:on
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
38 This turns on debugging information for the entire EDAC subsystem.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
49 occurring on your machine in human-readable form.
57 depends on ACPI_APEI_GHES && (EDAC=y)
80 depends on AMD_NB && EDAC_DECODE_MCE
82 Support for error detection and correction of DRAM ECC errors on
105 depends on (ARCH_ALPINE || COMPILE_TEST)
112 depends on PCI && X86_32
114 Support for error detection and correction on the AMD 76x
119 depends on PCI && X86_32
121 Support for error detection and correction on the Intel
126 depends on PCI && X86
128 Support for error detection and correction on the Intel
133 depends on PCI && X86_32
134 depends on BROKEN
136 Support for error detection and correction on the Intel
141 depends on PCI && X86_32
143 Support for error detection and correction on the Intel
148 depends on PCI && X86
150 Support for error detection and correction on the Intel
155 depends on PCI && X86
157 Support for error detection and correction on the Intel
162 depends on PCI && X86
164 Support for error detection and correction on the Intel
169 depends on PCI && X86
171 Support for error detection and correction on the Intel
176 depends on PCI && X86
178 Support for error detection and correction on the Intel
183 depends on PCI && X86
190 depends on PCI && X86 && X86_MCE_INTEL
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
199 depends on PCI && X86_32
201 Support for error detection and correction on the Intel
206 depends on PCI && X86_32
208 Support for error detection and correction on the Radisys
213 depends on X86 && PCI
220 depends on X86 && PCI
227 depends on X86 && PCI
234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
241 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
242 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
253 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
254 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
265 depends on PCI && X86_64 && X86_MCE_INTEL
268 Support for error detection and correction on the Intel
270 first used on the Apollo Lake platform and Denverton
271 micro-server but may appear on others in the future.
275 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
276 depends on X86_64 && X86_MCE_INTEL
278 Support for error detection and correction on the Intel
280 This In-Band ECC is first used on the Elkhart Lake SoC but
281 may appear on others in the future.
285 depends on FSL_SOC && EDAC=y
287 Support for error detection and correction on the Freescale
292 depends on ARCH_LAYERSCAPE || SOC_LS1021A
294 Support for error detection and correction on Freescale memory
295 controllers on Layerscape SoCs.
299 depends on PPC_PASEMI && PCI
301 Support for error detection and correction on PA Semi
306 depends on PPC_CELL_COMMON
308 Support for error detection and correction on the
310 on platform without a hypervisor
314 depends on 4xx
316 This enables support for EDAC on the ECC memory used
323 depends on PCI && PPC_MAPLE
325 Support for error detection and correction on the
328 on some machine other than Maple.
332 depends on PCI && PPC_MAPLE
334 Support for error detection and correction on the
337 on some machine other than Maple.
341 depends on PPC64
343 Support for error detection and correction on the
350 depends on ARCH_HIGHBANK
352 Support for error detection and correction on the
357 depends on ARCH_HIGHBANK
359 Support for error detection and correction on the
364 depends on CPU_CAVIUM_OCTEON
366 Support for error detection and correction on the primary caches of
371 depends on CAVIUM_OCTEON_SOC
373 Support for error detection and correction on the
378 depends on CAVIUM_OCTEON_SOC
380 Support for error detection and correction on the
385 depends on PCI && CAVIUM_OCTEON_SOC
387 Support for error detection and correction on the
392 depends on ARM64
393 depends on PCI
395 Support for error detection and correction on the
402 depends on EDAC=y && ARCH_INTEL_SOCFPGA
404 Support for error detection and correction on the
410 depends on EDAC_ALTERA=y
412 Support for error detection and correction on the
419 depends on EDAC_ALTERA=y && CACHE_L2X0
421 Support for error detection and correction on the
426 bool "Altera On-Chip RAM ECC"
427 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
429 Support for error detection and correction on the
430 Altera On-Chip RAM Memory for Altera SoCs.
434 depends on EDAC_ALTERA=y
436 Support for error detection and correction on the
441 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
443 Support for error detection and correction on the
448 depends on EDAC_ALTERA=y && PL330_DMA=y
450 Support for error detection and correction on the
455 depends on EDAC_ALTERA=y && USB_DWC2
457 Support for error detection and correction on the
462 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
464 Support for error detection and correction on the
469 depends on EDAC_ALTERA=y && MMC_DW
471 Support for error detection and correction on the
476 depends on EDAC=y && SIFIVE_CCACHE
478 Support for error detection and correction on the SiFive SoCs.
482 depends on MACH_MVEBU_V7
484 Support for error correction and detection on the Marvell Aramada XP
489 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
491 Support for error detection and correction on the Synopsys DDR
496 depends on (ARM64 || COMPILE_TEST)
498 Support for error detection and correction on the
503 depends on ARCH_KEYSTONE || SOC_DRA7XX
505 Support for error detection and correction on the TI SoCs.
509 depends on ARCH_QCOM && QCOM_LLCC
511 Support for error detection and correction on the
523 depends on ARCH_ASPEED
525 Support for error detection and correction on the Aspeed AST BMC SoC.
532 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
534 Support for error detection and correction on the
539 depends on ARM64
541 Support for error detection and correction on the