Lines Matching full:and
4 # Licensed and distributed under the GPL
13 tristate "EDAC (Error Detection And Correction) reporting"
40 levels are 0-4 (from low to high) and by default it is set to 2.
69 It should be noticed that keeping both GHES and a hardware-driven
82 Support for error detection and correction of DRAM ECC errors on
88 AMD CPUs up to and excluding family 0x17 provide for Memory
90 module allows the operator/user to inject Uncorrectable and
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
114 Support for error detection and correction on the AMD 76x
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
128 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
150 Support for error detection and correction on the Intel
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
171 Support for error detection and correction on the Intel
178 Support for error detection and correction on the Intel
185 Support for error detection and correction the Intel
192 Support for error detection and correction the Intel
195 and Xeon 55xx processors.
201 Support for error detection and correction on the Intel
208 Support for error detection and correction on the Radisys
215 Support for error detection and correction the Intel
222 Support for error detection and correction the Intel
229 Support for error detection and correction the Intel
236 Support for error detection and correction the Intel
237 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
246 Support for error detection and correction the Intel
258 Support for error detection and correction the Intel
268 Support for error detection and correction on the Intel
270 first used on the Apollo Lake platform and Denverton
278 Support for error detection and correction on the Intel
287 Support for error detection and correction on the Freescale
294 Support for error detection and correction on Freescale memory
301 Support for error detection and correction on PA Semi
308 Support for error detection and correction on the
319 440SP, 440SPe, 460EX, 460GT and 460SX.
325 Support for error detection and correction on the
334 Support for error detection and correction on the
343 Support for error detection and correction on the
344 IBM CPC925 Bridge and Memory Controller, which is
352 Support for error detection and correction on the
359 Support for error detection and correction on the
366 Support for error detection and correction on the primary caches of
373 Support for error detection and correction on the
380 Support for error detection and correction on the
387 Support for error detection and correction on the
395 Support for error detection and correction on the
397 Coherent Processor Interconnect (CCPI) and L2 cache
404 Support for error detection and correction on the
412 Support for error detection and correction on the
421 Support for error detection and correction on the
429 Support for error detection and correction on the
436 Support for error detection and correction on the
443 Support for error detection and correction on the
450 Support for error detection and correction on the
457 Support for error detection and correction on the
464 Support for error detection and correction on the
471 Support for error detection and correction on the
478 Support for error detection and correction on the SiFive SoCs.
481 bool "Marvell Armada XP DDR and L2 Cache ECC"
484 Support for error correction and detection on the Marvell Aramada XP
485 DDR RAM and L2 cache controllers.
491 Support for error detection and correction on the Synopsys DDR
498 Support for error detection and correction on the
505 Support for error detection and correction on the TI SoCs.
511 Support for error detection and correction on the
514 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
516 of Tag RAM and Data RAM.
518 For debugging issues having to do with stability and overall system
525 Support for error detection and correction on the Aspeed AST BMC SoC.
534 Support for error detection and correction on the
541 Support for error detection and correction on the