Lines Matching refs:tr_req
2878 struct cppi5_tr_type1_t *tr_req = NULL; in udma_prep_slave_sg_tr() local
2907 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_tr()
2921 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, in udma_prep_slave_sg_tr()
2923 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_slave_sg_tr()
2926 tr_req[tr_idx].addr = sg_addr; in udma_prep_slave_sg_tr()
2927 tr_req[tr_idx].icnt0 = tr0_cnt0; in udma_prep_slave_sg_tr()
2928 tr_req[tr_idx].icnt1 = tr0_cnt1; in udma_prep_slave_sg_tr()
2929 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_slave_sg_tr()
2933 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, in udma_prep_slave_sg_tr()
2936 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_slave_sg_tr()
2939 tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0; in udma_prep_slave_sg_tr()
2940 tr_req[tr_idx].icnt0 = tr1_cnt0; in udma_prep_slave_sg_tr()
2941 tr_req[tr_idx].icnt1 = 1; in udma_prep_slave_sg_tr()
2942 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_slave_sg_tr()
2949 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_tr()
2962 struct cppi5_tr_type15_t *tr_req = NULL; in udma_prep_slave_sg_triggered_tr() local
3039 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_triggered_tr()
3055 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, false, in udma_prep_slave_sg_triggered_tr()
3057 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_slave_sg_triggered_tr()
3058 cppi5_tr_set_trigger(&tr_req[tr_idx].flags, in udma_prep_slave_sg_triggered_tr()
3064 tr_req[tr_idx].addr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3065 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3066 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3067 tr_req[tr_idx].icnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3068 tr_req[tr_idx].icnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3069 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3071 tr_req[tr_idx].daddr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3072 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3073 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3074 tr_req[tr_idx].dicnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3075 tr_req[tr_idx].dicnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3076 tr_req[tr_idx].ddim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3077 tr_req[tr_idx].ddim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3078 tr_req[tr_idx].ddim3 = trigger_size * tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3080 tr_req[tr_idx].addr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3081 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3082 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3083 tr_req[tr_idx].icnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3084 tr_req[tr_idx].icnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3085 tr_req[tr_idx].dim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3086 tr_req[tr_idx].dim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3087 tr_req[tr_idx].dim3 = trigger_size * tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3089 tr_req[tr_idx].daddr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3090 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3091 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3092 tr_req[tr_idx].dicnt2 = tr0_cnt2; in udma_prep_slave_sg_triggered_tr()
3093 tr_req[tr_idx].dicnt3 = tr0_cnt3; in udma_prep_slave_sg_triggered_tr()
3094 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3100 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE15, in udma_prep_slave_sg_triggered_tr()
3103 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_slave_sg_triggered_tr()
3105 cppi5_tr_set_trigger(&tr_req[tr_idx].flags, in udma_prep_slave_sg_triggered_tr()
3112 tr_req[tr_idx].addr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3113 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3114 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3115 tr_req[tr_idx].icnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3116 tr_req[tr_idx].icnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3117 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3119 tr_req[tr_idx].daddr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3120 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3121 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3122 tr_req[tr_idx].dicnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3123 tr_req[tr_idx].dicnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3124 tr_req[tr_idx].ddim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3125 tr_req[tr_idx].ddim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3127 tr_req[tr_idx].addr = sg_addr; in udma_prep_slave_sg_triggered_tr()
3128 tr_req[tr_idx].icnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3129 tr_req[tr_idx].icnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3130 tr_req[tr_idx].icnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3131 tr_req[tr_idx].icnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3132 tr_req[tr_idx].dim1 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3133 tr_req[tr_idx].dim2 = trigger_size; in udma_prep_slave_sg_triggered_tr()
3135 tr_req[tr_idx].daddr = dev_addr; in udma_prep_slave_sg_triggered_tr()
3136 tr_req[tr_idx].dicnt0 = tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3137 tr_req[tr_idx].dicnt1 = tr_cnt1; in udma_prep_slave_sg_triggered_tr()
3138 tr_req[tr_idx].dicnt2 = tr1_cnt2; in udma_prep_slave_sg_triggered_tr()
3139 tr_req[tr_idx].dicnt3 = 1; in udma_prep_slave_sg_triggered_tr()
3140 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3148 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_triggered_tr()
3470 struct cppi5_tr_type1_t *tr_req; in udma_prep_dma_cyclic_tr() local
3490 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_cyclic_tr()
3500 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false, in udma_prep_dma_cyclic_tr()
3503 tr_req[tr_idx].addr = period_addr; in udma_prep_dma_cyclic_tr()
3504 tr_req[tr_idx].icnt0 = tr0_cnt0; in udma_prep_dma_cyclic_tr()
3505 tr_req[tr_idx].icnt1 = tr0_cnt1; in udma_prep_dma_cyclic_tr()
3506 tr_req[tr_idx].dim1 = tr0_cnt0; in udma_prep_dma_cyclic_tr()
3509 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_dma_cyclic_tr()
3513 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, in udma_prep_dma_cyclic_tr()
3517 tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0; in udma_prep_dma_cyclic_tr()
3518 tr_req[tr_idx].icnt0 = tr1_cnt0; in udma_prep_dma_cyclic_tr()
3519 tr_req[tr_idx].icnt1 = 1; in udma_prep_dma_cyclic_tr()
3520 tr_req[tr_idx].dim1 = tr1_cnt0; in udma_prep_dma_cyclic_tr()
3524 cppi5_tr_csf_set(&tr_req[tr_idx].flags, in udma_prep_dma_cyclic_tr()
3674 struct cppi5_tr_type15_t *tr_req; in udma_prep_dma_memcpy() local
3710 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_memcpy()
3712 cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true, in udma_prep_dma_memcpy()
3714 cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_dma_memcpy()
3716 tr_req[0].addr = src; in udma_prep_dma_memcpy()
3717 tr_req[0].icnt0 = tr0_cnt0; in udma_prep_dma_memcpy()
3718 tr_req[0].icnt1 = tr0_cnt1; in udma_prep_dma_memcpy()
3719 tr_req[0].icnt2 = 1; in udma_prep_dma_memcpy()
3720 tr_req[0].icnt3 = 1; in udma_prep_dma_memcpy()
3721 tr_req[0].dim1 = tr0_cnt0; in udma_prep_dma_memcpy()
3723 tr_req[0].daddr = dest; in udma_prep_dma_memcpy()
3724 tr_req[0].dicnt0 = tr0_cnt0; in udma_prep_dma_memcpy()
3725 tr_req[0].dicnt1 = tr0_cnt1; in udma_prep_dma_memcpy()
3726 tr_req[0].dicnt2 = 1; in udma_prep_dma_memcpy()
3727 tr_req[0].dicnt3 = 1; in udma_prep_dma_memcpy()
3728 tr_req[0].ddim1 = tr0_cnt0; in udma_prep_dma_memcpy()
3731 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true, in udma_prep_dma_memcpy()
3733 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT); in udma_prep_dma_memcpy()
3735 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0; in udma_prep_dma_memcpy()
3736 tr_req[1].icnt0 = tr1_cnt0; in udma_prep_dma_memcpy()
3737 tr_req[1].icnt1 = 1; in udma_prep_dma_memcpy()
3738 tr_req[1].icnt2 = 1; in udma_prep_dma_memcpy()
3739 tr_req[1].icnt3 = 1; in udma_prep_dma_memcpy()
3741 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0; in udma_prep_dma_memcpy()
3742 tr_req[1].dicnt0 = tr1_cnt0; in udma_prep_dma_memcpy()
3743 tr_req[1].dicnt1 = 1; in udma_prep_dma_memcpy()
3744 tr_req[1].dicnt2 = 1; in udma_prep_dma_memcpy()
3745 tr_req[1].dicnt3 = 1; in udma_prep_dma_memcpy()
3748 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, in udma_prep_dma_memcpy()
5057 struct cppi5_tr_type1_t *tr_req; in udma_setup_rx_flush() local
5104 tr_req = hwdesc->tr_req_base; in udma_setup_rx_flush()
5105 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, in udma_setup_rx_flush()
5107 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); in udma_setup_rx_flush()
5109 tr_req->addr = rx_flush->buffer_paddr; in udma_setup_rx_flush()
5110 tr_req->icnt0 = rx_flush->buffer_size; in udma_setup_rx_flush()
5111 tr_req->icnt1 = 1; in udma_setup_rx_flush()