Lines Matching +full:sci +full:- +full:rm +full:- +full:range +full:- +full:rchan
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/dma-mapping.h>
26 #include <linux/soc/ti/k3-ringacc.h>
29 #include <linux/dma/k3-event-router.h>
30 #include <linux/dma/ti-cppi5.h>
32 #include "../virt-dma.h"
33 #include "k3-udma.h"
34 #include "k3-psil-priv.h"
288 struct udma_rchan *rchan; member
356 if (!uc->tchan) in udma_tchanrt_read()
358 return udma_read(uc->tchan->reg_rt, reg); in udma_tchanrt_read()
363 if (!uc->tchan) in udma_tchanrt_write()
365 udma_write(uc->tchan->reg_rt, reg, val); in udma_tchanrt_write()
371 if (!uc->tchan) in udma_tchanrt_update_bits()
373 udma_update_bits(uc->tchan->reg_rt, reg, mask, val); in udma_tchanrt_update_bits()
379 if (!uc->rchan) in udma_rchanrt_read()
381 return udma_read(uc->rchan->reg_rt, reg); in udma_rchanrt_read()
386 if (!uc->rchan) in udma_rchanrt_write()
388 udma_write(uc->rchan->reg_rt, reg, val); in udma_rchanrt_write()
394 if (!uc->rchan) in udma_rchanrt_update_bits()
396 udma_update_bits(uc->rchan->reg_rt, reg, mask, val); in udma_rchanrt_update_bits()
401 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in navss_psil_pair()
404 return tisci_rm->tisci_psil_ops->pair(tisci_rm->tisci, in navss_psil_pair()
405 tisci_rm->tisci_navss_dev_id, in navss_psil_pair()
412 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in navss_psil_unpair()
415 return tisci_rm->tisci_psil_ops->unpair(tisci_rm->tisci, in navss_psil_unpair()
416 tisci_rm->tisci_navss_dev_id, in navss_psil_unpair()
422 struct device *chan_dev = &chan->dev->device; in k3_configure_chan_coherency()
426 chan->dev->chan_dma_dev = false; in k3_configure_chan_coherency()
428 chan_dev->dma_coherent = false; in k3_configure_chan_coherency()
429 chan_dev->dma_parms = NULL; in k3_configure_chan_coherency()
431 chan->dev->chan_dma_dev = true; in k3_configure_chan_coherency()
433 chan_dev->dma_coherent = true; in k3_configure_chan_coherency()
435 chan_dev->dma_parms = chan_dev->parent->dma_parms; in k3_configure_chan_coherency()
437 dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel); in k3_configure_chan_coherency()
439 chan_dev->dma_coherent = false; in k3_configure_chan_coherency()
440 chan_dev->dma_parms = NULL; in k3_configure_chan_coherency()
448 for (i = 0; i < tpl_map->levels; i++) { in udma_get_chan_tpl_index()
449 if (chan_id >= tpl_map->start_idx[i]) in udma_get_chan_tpl_index()
458 memset(&uc->config, 0, sizeof(uc->config)); in udma_reset_uchan()
459 uc->config.remote_thread_id = -1; in udma_reset_uchan()
460 uc->config.mapped_channel_id = -1; in udma_reset_uchan()
461 uc->config.default_flow_id = -1; in udma_reset_uchan()
462 uc->state = UDMA_CHAN_IS_IDLE; in udma_reset_uchan()
467 struct device *dev = uc->ud->dev; in udma_dump_chan_stdata()
471 if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) { in udma_dump_chan_stdata()
480 if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) { in udma_dump_chan_stdata()
481 dev_dbg(dev, "RCHAN State data:\n"); in udma_dump_chan_stdata()
493 return d->hwdesc[idx].cppi5_desc_paddr; in udma_curr_cppi5_desc_paddr()
498 return d->hwdesc[idx].cppi5_desc_vaddr; in udma_curr_cppi5_desc_vaddr()
504 struct udma_desc *d = uc->terminated_desc; in udma_udma_desc_from_paddr()
508 d->desc_idx); in udma_udma_desc_from_paddr()
515 d = uc->desc; in udma_udma_desc_from_paddr()
518 d->desc_idx); in udma_udma_desc_from_paddr()
530 if (uc->use_dma_pool) { in udma_free_hwdesc()
533 for (i = 0; i < d->hwdesc_count; i++) { in udma_free_hwdesc()
534 if (!d->hwdesc[i].cppi5_desc_vaddr) in udma_free_hwdesc()
537 dma_pool_free(uc->hdesc_pool, in udma_free_hwdesc()
538 d->hwdesc[i].cppi5_desc_vaddr, in udma_free_hwdesc()
539 d->hwdesc[i].cppi5_desc_paddr); in udma_free_hwdesc()
541 d->hwdesc[i].cppi5_desc_vaddr = NULL; in udma_free_hwdesc()
543 } else if (d->hwdesc[0].cppi5_desc_vaddr) { in udma_free_hwdesc()
544 dma_free_coherent(uc->dma_dev, d->hwdesc[0].cppi5_desc_size, in udma_free_hwdesc()
545 d->hwdesc[0].cppi5_desc_vaddr, in udma_free_hwdesc()
546 d->hwdesc[0].cppi5_desc_paddr); in udma_free_hwdesc()
548 d->hwdesc[0].cppi5_desc_vaddr = NULL; in udma_free_hwdesc()
559 spin_lock_irqsave(&ud->lock, flags); in udma_purge_desc_work()
560 list_splice_tail_init(&ud->desc_to_purge, &head); in udma_purge_desc_work()
561 spin_unlock_irqrestore(&ud->lock, flags); in udma_purge_desc_work()
564 struct udma_chan *uc = to_udma_chan(vd->tx.chan); in udma_purge_desc_work()
565 struct udma_desc *d = to_udma_desc(&vd->tx); in udma_purge_desc_work()
568 list_del(&vd->node); in udma_purge_desc_work()
573 if (!list_empty(&ud->desc_to_purge)) in udma_purge_desc_work()
574 schedule_work(&ud->purge_work); in udma_purge_desc_work()
579 struct udma_dev *ud = to_udma_dev(vd->tx.chan->device); in udma_desc_free()
580 struct udma_chan *uc = to_udma_chan(vd->tx.chan); in udma_desc_free()
581 struct udma_desc *d = to_udma_desc(&vd->tx); in udma_desc_free()
584 if (uc->terminated_desc == d) in udma_desc_free()
585 uc->terminated_desc = NULL; in udma_desc_free()
587 if (uc->use_dma_pool) { in udma_desc_free()
593 spin_lock_irqsave(&ud->lock, flags); in udma_desc_free()
594 list_add_tail(&vd->node, &ud->desc_to_purge); in udma_desc_free()
595 spin_unlock_irqrestore(&ud->lock, flags); in udma_desc_free()
597 schedule_work(&ud->purge_work); in udma_desc_free()
605 if (uc->tchan) in udma_is_chan_running()
607 if (uc->rchan) in udma_is_chan_running()
620 switch (uc->config.dir) { in udma_is_chan_paused()
645 return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; in udma_get_rx_flush_hwdesc_paddr()
650 struct udma_desc *d = uc->desc; in udma_push_to_ring()
654 switch (uc->config.dir) { in udma_push_to_ring()
656 ring = uc->rflow->fd_ring; in udma_push_to_ring()
660 ring = uc->tchan->t_ring; in udma_push_to_ring()
663 return -EINVAL; in udma_push_to_ring()
666 /* RX flush packet: idx == -1 is only passed in case of DEV_TO_MEM */ in udma_push_to_ring()
667 if (idx == -1) { in udma_push_to_ring()
680 if (uc->config.dir != DMA_DEV_TO_MEM) in udma_desc_is_rx_flush()
694 switch (uc->config.dir) { in udma_pop_from_ring()
696 ring = uc->rflow->r_ring; in udma_pop_from_ring()
700 ring = uc->tchan->tc_ring; in udma_pop_from_ring()
703 return -ENOENT; in udma_pop_from_ring()
718 return -ENOENT; in udma_pop_from_ring()
728 switch (uc->config.dir) { in udma_reset_rings()
730 if (uc->rchan) { in udma_reset_rings()
731 ring1 = uc->rflow->fd_ring; in udma_reset_rings()
732 ring2 = uc->rflow->r_ring; in udma_reset_rings()
737 if (uc->tchan) { in udma_reset_rings()
738 ring1 = uc->tchan->t_ring; in udma_reset_rings()
739 ring2 = uc->tchan->tc_ring; in udma_reset_rings()
753 if (uc->terminated_desc) { in udma_reset_rings()
754 udma_desc_free(&uc->terminated_desc->vd); in udma_reset_rings()
755 uc->terminated_desc = NULL; in udma_reset_rings()
761 if (uc->desc->dir == DMA_DEV_TO_MEM) { in udma_decrement_byte_counters()
768 if (!uc->bchan) in udma_decrement_byte_counters()
777 if (uc->tchan) { in udma_reset_counters()
787 if (!uc->bchan) { in udma_reset_counters()
793 if (uc->rchan) { in udma_reset_counters()
810 switch (uc->config.dir) { in udma_reset_chan()
824 return -EINVAL; in udma_reset_chan()
830 /* Hard reset: re-initialize the channel to reset */ in udma_reset_chan()
835 memcpy(&ucc_backup, &uc->config, sizeof(uc->config)); in udma_reset_chan()
836 uc->ud->ddev.device_free_chan_resources(&uc->vc.chan); in udma_reset_chan()
839 memcpy(&uc->config, &ucc_backup, sizeof(uc->config)); in udma_reset_chan()
840 ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan); in udma_reset_chan()
846 * the rchan. in udma_reset_chan()
848 if (uc->config.dir == DMA_DEV_TO_MEM) in udma_reset_chan()
854 uc->state = UDMA_CHAN_IS_IDLE; in udma_reset_chan()
861 struct udma_chan_config *ucc = &uc->config; in udma_start_desc()
863 if (uc->ud->match_data->type == DMA_TYPE_UDMA && ucc->pkt_mode && in udma_start_desc()
864 (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) { in udma_start_desc()
870 * PKTDMA supports pre-linked descriptor and cyclic is not in udma_start_desc()
873 for (i = 0; i < uc->desc->sglen; i++) in udma_start_desc()
883 if (uc->config.ep_type == PSIL_EP_NATIVE) in udma_chan_needs_reconfiguration()
887 if (memcmp(&uc->static_tr, &uc->desc->static_tr, sizeof(uc->static_tr))) in udma_chan_needs_reconfiguration()
895 struct virt_dma_desc *vd = vchan_next_desc(&uc->vc); in udma_start()
898 uc->desc = NULL; in udma_start()
899 return -ENOENT; in udma_start()
902 list_del(&vd->node); in udma_start()
904 uc->desc = to_udma_desc(&vd->tx); in udma_start()
918 switch (uc->desc->dir) { in udma_start()
921 if (uc->config.ep_type == PSIL_EP_PDMA_XY) { in udma_start()
922 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | in udma_start()
923 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); in udma_start()
925 uc->ud->match_data; in udma_start()
927 if (uc->config.enable_acc32) in udma_start()
929 if (uc->config.enable_burst) in udma_start()
938 PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt, in udma_start()
939 match_data->statictr_z_mask)); in udma_start()
942 memcpy(&uc->static_tr, &uc->desc->static_tr, in udma_start()
943 sizeof(uc->static_tr)); in udma_start()
956 if (uc->config.ep_type == PSIL_EP_PDMA_XY) { in udma_start()
957 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) | in udma_start()
958 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize); in udma_start()
960 if (uc->config.enable_acc32) in udma_start()
962 if (uc->config.enable_burst) in udma_start()
970 memcpy(&uc->static_tr, &uc->desc->static_tr, in udma_start()
971 sizeof(uc->static_tr)); in udma_start()
990 return -EINVAL; in udma_start()
993 uc->state = UDMA_CHAN_IS_ACTIVE; in udma_start()
1001 enum udma_chan_state old_state = uc->state; in udma_stop()
1003 uc->state = UDMA_CHAN_IS_TERMINATING; in udma_stop()
1004 reinit_completion(&uc->teardown_completed); in udma_stop()
1006 switch (uc->config.dir) { in udma_stop()
1008 if (!uc->cyclic && !uc->desc) in udma_stop()
1009 udma_push_to_ring(uc, -1); in udma_stop()
1029 uc->state = old_state; in udma_stop()
1030 complete_all(&uc->teardown_completed); in udma_stop()
1031 return -EINVAL; in udma_stop()
1039 struct udma_desc *d = uc->desc; in udma_cyclic_packet_elapsed()
1042 h_desc = d->hwdesc[d->desc_idx].cppi5_desc_vaddr; in udma_cyclic_packet_elapsed()
1044 udma_push_to_ring(uc, d->desc_idx); in udma_cyclic_packet_elapsed()
1045 d->desc_idx = (d->desc_idx + 1) % d->sglen; in udma_cyclic_packet_elapsed()
1050 struct cppi5_host_desc_t *h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_fetch_epib()
1052 memcpy(d->metadata, h_desc->epib, d->metadata_size); in udma_fetch_epib()
1065 if (uc->config.ep_type == PSIL_EP_NATIVE || in udma_is_desc_really_done()
1066 uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT)) in udma_is_desc_really_done()
1074 uc->tx_drain.residue = bcnt - peer_bcnt; in udma_is_desc_really_done()
1075 uc->tx_drain.tstamp = ktime_get(); in udma_is_desc_really_done()
1092 if (uc->desc) { in udma_check_tx_completion()
1094 residue_diff = uc->tx_drain.residue; in udma_check_tx_completion()
1095 time_diff = uc->tx_drain.tstamp; in udma_check_tx_completion()
1100 desc_done = udma_is_desc_really_done(uc, uc->desc); in udma_check_tx_completion()
1108 time_diff = ktime_sub(uc->tx_drain.tstamp, in udma_check_tx_completion()
1110 residue_diff -= uc->tx_drain.residue; in udma_check_tx_completion()
1119 uc->tx_drain.residue; in udma_check_tx_completion()
1122 schedule_delayed_work(&uc->tx_drain.work, HZ); in udma_check_tx_completion()
1131 if (uc->desc) { in udma_check_tx_completion()
1132 struct udma_desc *d = uc->desc; in udma_check_tx_completion()
1134 udma_decrement_byte_counters(uc, d->residue); in udma_check_tx_completion()
1136 vchan_cookie_complete(&d->vd); in udma_check_tx_completion()
1153 spin_lock(&uc->vc.lock); in udma_ring_irq_handler()
1157 complete_all(&uc->teardown_completed); in udma_ring_irq_handler()
1159 if (uc->terminated_desc) { in udma_ring_irq_handler()
1160 udma_desc_free(&uc->terminated_desc->vd); in udma_ring_irq_handler()
1161 uc->terminated_desc = NULL; in udma_ring_irq_handler()
1164 if (!uc->desc) in udma_ring_irq_handler()
1174 d->desc_idx); in udma_ring_irq_handler()
1176 dev_err(uc->ud->dev, "not matching descriptors!\n"); in udma_ring_irq_handler()
1180 if (d == uc->desc) { in udma_ring_irq_handler()
1182 if (uc->cyclic) { in udma_ring_irq_handler()
1184 vchan_cyclic_callback(&d->vd); in udma_ring_irq_handler()
1187 udma_decrement_byte_counters(uc, d->residue); in udma_ring_irq_handler()
1189 vchan_cookie_complete(&d->vd); in udma_ring_irq_handler()
1191 schedule_delayed_work(&uc->tx_drain.work, in udma_ring_irq_handler()
1200 dma_cookie_complete(&d->vd.tx); in udma_ring_irq_handler()
1204 spin_unlock(&uc->vc.lock); in udma_ring_irq_handler()
1214 spin_lock(&uc->vc.lock); in udma_udma_irq_handler()
1215 d = uc->desc; in udma_udma_irq_handler()
1217 d->tr_idx = (d->tr_idx + 1) % d->sglen; in udma_udma_irq_handler()
1219 if (uc->cyclic) { in udma_udma_irq_handler()
1220 vchan_cyclic_callback(&d->vd); in udma_udma_irq_handler()
1223 udma_decrement_byte_counters(uc, d->residue); in udma_udma_irq_handler()
1225 vchan_cookie_complete(&d->vd); in udma_udma_irq_handler()
1229 spin_unlock(&uc->vc.lock); in udma_udma_irq_handler()
1235 * __udma_alloc_gp_rflow_range - alloc range of GP RX flows
1240 * Allocate range of RX flow ids for future use, those flows can be requested
1241 * only using explicit flow id number. if @from is set to -1 it will try to find
1242 * first free range. if @from is positive value it will force allocation only
1243 * of the specified range of flows.
1245 * Returns -ENOMEM if can't find free range.
1246 * -EEXIST if requested range is busy.
1247 * -EINVAL if wrong input values passed.
1257 tmp_from = ud->rchan_cnt; in __udma_alloc_gp_rflow_range()
1259 if (tmp_from < ud->rchan_cnt) in __udma_alloc_gp_rflow_range()
1260 return -EINVAL; in __udma_alloc_gp_rflow_range()
1262 if (tmp_from + cnt > ud->rflow_cnt) in __udma_alloc_gp_rflow_range()
1263 return -EINVAL; in __udma_alloc_gp_rflow_range()
1265 bitmap_or(tmp, ud->rflow_gp_map, ud->rflow_gp_map_allocated, in __udma_alloc_gp_rflow_range()
1266 ud->rflow_cnt); in __udma_alloc_gp_rflow_range()
1269 ud->rflow_cnt, in __udma_alloc_gp_rflow_range()
1271 if (start >= ud->rflow_cnt) in __udma_alloc_gp_rflow_range()
1272 return -ENOMEM; in __udma_alloc_gp_rflow_range()
1275 return -EEXIST; in __udma_alloc_gp_rflow_range()
1277 bitmap_set(ud->rflow_gp_map_allocated, start, cnt); in __udma_alloc_gp_rflow_range()
1283 if (from < ud->rchan_cnt) in __udma_free_gp_rflow_range()
1284 return -EINVAL; in __udma_free_gp_rflow_range()
1285 if (from + cnt > ud->rflow_cnt) in __udma_free_gp_rflow_range()
1286 return -EINVAL; in __udma_free_gp_rflow_range()
1288 bitmap_clear(ud->rflow_gp_map_allocated, from, cnt); in __udma_free_gp_rflow_range()
1297 * TI-SCI FW will perform additional permission check ant way, it's in __udma_get_rflow()
1301 if (id < 0 || id >= ud->rflow_cnt) in __udma_get_rflow()
1302 return ERR_PTR(-ENOENT); in __udma_get_rflow()
1304 if (test_bit(id, ud->rflow_in_use)) in __udma_get_rflow()
1305 return ERR_PTR(-ENOENT); in __udma_get_rflow()
1307 if (ud->rflow_gp_map) { in __udma_get_rflow()
1309 if (!test_bit(id, ud->rflow_gp_map) && in __udma_get_rflow()
1310 !test_bit(id, ud->rflow_gp_map_allocated)) in __udma_get_rflow()
1311 return ERR_PTR(-EINVAL); in __udma_get_rflow()
1314 dev_dbg(ud->dev, "get rflow%d\n", id); in __udma_get_rflow()
1315 set_bit(id, ud->rflow_in_use); in __udma_get_rflow()
1316 return &ud->rflows[id]; in __udma_get_rflow()
1321 if (!test_bit(rflow->id, ud->rflow_in_use)) { in __udma_put_rflow()
1322 dev_err(ud->dev, "attempt to put unused rflow%d\n", rflow->id); in __udma_put_rflow()
1326 dev_dbg(ud->dev, "put rflow%d\n", rflow->id); in __udma_put_rflow()
1327 clear_bit(rflow->id, ud->rflow_in_use); in __udma_put_rflow()
1336 if (test_bit(id, ud->res##_map)) { \
1337 dev_err(ud->dev, "res##%d is in use\n", id); \
1338 return ERR_PTR(-ENOENT); \
1343 if (tpl >= ud->res##_tpl.levels) \
1344 tpl = ud->res##_tpl.levels - 1; \
1346 start = ud->res##_tpl.start_idx[tpl]; \
1348 id = find_next_zero_bit(ud->res##_map, ud->res##_cnt, \
1350 if (id == ud->res##_cnt) { \
1351 return ERR_PTR(-ENOENT); \
1355 set_bit(id, ud->res##_map); \
1356 return &ud->res##s[id]; \
1361 UDMA_RESERVE_RESOURCE(rchan);
1365 struct udma_dev *ud = uc->ud; in bcdma_get_bchan()
1369 if (uc->bchan) { in bcdma_get_bchan()
1370 dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n", in bcdma_get_bchan()
1371 uc->id, uc->bchan->id); in bcdma_get_bchan()
1379 if (uc->config.tr_trigger_type) in bcdma_get_bchan()
1382 tpl = ud->bchan_tpl.levels - 1; in bcdma_get_bchan()
1384 uc->bchan = __udma_reserve_bchan(ud, tpl, -1); in bcdma_get_bchan()
1385 if (IS_ERR(uc->bchan)) { in bcdma_get_bchan()
1386 ret = PTR_ERR(uc->bchan); in bcdma_get_bchan()
1387 uc->bchan = NULL; in bcdma_get_bchan()
1391 uc->tchan = uc->bchan; in bcdma_get_bchan()
1398 struct udma_dev *ud = uc->ud; in udma_get_tchan()
1401 if (uc->tchan) { in udma_get_tchan()
1402 dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n", in udma_get_tchan()
1403 uc->id, uc->tchan->id); in udma_get_tchan()
1408 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. in udma_get_tchan()
1412 uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, in udma_get_tchan()
1413 uc->config.mapped_channel_id); in udma_get_tchan()
1414 if (IS_ERR(uc->tchan)) { in udma_get_tchan()
1415 ret = PTR_ERR(uc->tchan); in udma_get_tchan()
1416 uc->tchan = NULL; in udma_get_tchan()
1420 if (ud->tflow_cnt) { in udma_get_tchan()
1424 if (uc->config.default_flow_id >= 0) in udma_get_tchan()
1425 tflow_id = uc->config.default_flow_id; in udma_get_tchan()
1427 tflow_id = uc->tchan->id; in udma_get_tchan()
1429 if (test_bit(tflow_id, ud->tflow_map)) { in udma_get_tchan()
1430 dev_err(ud->dev, "tflow%d is in use\n", tflow_id); in udma_get_tchan()
1431 clear_bit(uc->tchan->id, ud->tchan_map); in udma_get_tchan()
1432 uc->tchan = NULL; in udma_get_tchan()
1433 return -ENOENT; in udma_get_tchan()
1436 uc->tchan->tflow_id = tflow_id; in udma_get_tchan()
1437 set_bit(tflow_id, ud->tflow_map); in udma_get_tchan()
1439 uc->tchan->tflow_id = -1; in udma_get_tchan()
1447 struct udma_dev *ud = uc->ud; in udma_get_rchan()
1450 if (uc->rchan) { in udma_get_rchan()
1451 dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n", in udma_get_rchan()
1452 uc->id, uc->rchan->id); in udma_get_rchan()
1457 * mapped_channel_id is -1 for UDMA, BCDMA and PKTDMA unmapped channels. in udma_get_rchan()
1461 uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, in udma_get_rchan()
1462 uc->config.mapped_channel_id); in udma_get_rchan()
1463 if (IS_ERR(uc->rchan)) { in udma_get_rchan()
1464 ret = PTR_ERR(uc->rchan); in udma_get_rchan()
1465 uc->rchan = NULL; in udma_get_rchan()
1474 struct udma_dev *ud = uc->ud; in udma_get_chan_pair()
1477 if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) { in udma_get_chan_pair()
1478 dev_info(ud->dev, "chan%d: already have %d pair allocated\n", in udma_get_chan_pair()
1479 uc->id, uc->tchan->id); in udma_get_chan_pair()
1483 if (uc->tchan) { in udma_get_chan_pair()
1484 dev_err(ud->dev, "chan%d: already have tchan%d allocated\n", in udma_get_chan_pair()
1485 uc->id, uc->tchan->id); in udma_get_chan_pair()
1486 return -EBUSY; in udma_get_chan_pair()
1487 } else if (uc->rchan) { in udma_get_chan_pair()
1488 dev_err(ud->dev, "chan%d: already have rchan%d allocated\n", in udma_get_chan_pair()
1489 uc->id, uc->rchan->id); in udma_get_chan_pair()
1490 return -EBUSY; in udma_get_chan_pair()
1494 end = min(ud->tchan_cnt, ud->rchan_cnt); in udma_get_chan_pair()
1497 * Note: in UDMAP the channel TPL is symmetric between tchan and rchan in udma_get_chan_pair()
1499 chan_id = ud->tchan_tpl.start_idx[ud->tchan_tpl.levels - 1]; in udma_get_chan_pair()
1501 if (!test_bit(chan_id, ud->tchan_map) && in udma_get_chan_pair()
1502 !test_bit(chan_id, ud->rchan_map)) in udma_get_chan_pair()
1507 return -ENOENT; in udma_get_chan_pair()
1509 set_bit(chan_id, ud->tchan_map); in udma_get_chan_pair()
1510 set_bit(chan_id, ud->rchan_map); in udma_get_chan_pair()
1511 uc->tchan = &ud->tchans[chan_id]; in udma_get_chan_pair()
1512 uc->rchan = &ud->rchans[chan_id]; in udma_get_chan_pair()
1515 uc->tchan->tflow_id = -1; in udma_get_chan_pair()
1522 struct udma_dev *ud = uc->ud; in udma_get_rflow()
1525 if (!uc->rchan) { in udma_get_rflow()
1526 dev_err(ud->dev, "chan%d: does not have rchan??\n", uc->id); in udma_get_rflow()
1527 return -EINVAL; in udma_get_rflow()
1530 if (uc->rflow) { in udma_get_rflow()
1531 dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n", in udma_get_rflow()
1532 uc->id, uc->rflow->id); in udma_get_rflow()
1536 uc->rflow = __udma_get_rflow(ud, flow_id); in udma_get_rflow()
1537 if (IS_ERR(uc->rflow)) { in udma_get_rflow()
1538 ret = PTR_ERR(uc->rflow); in udma_get_rflow()
1539 uc->rflow = NULL; in udma_get_rflow()
1548 struct udma_dev *ud = uc->ud; in bcdma_put_bchan()
1550 if (uc->bchan) { in bcdma_put_bchan()
1551 dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id, in bcdma_put_bchan()
1552 uc->bchan->id); in bcdma_put_bchan()
1553 clear_bit(uc->bchan->id, ud->bchan_map); in bcdma_put_bchan()
1554 uc->bchan = NULL; in bcdma_put_bchan()
1555 uc->tchan = NULL; in bcdma_put_bchan()
1561 struct udma_dev *ud = uc->ud; in udma_put_rchan()
1563 if (uc->rchan) { in udma_put_rchan()
1564 dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id, in udma_put_rchan()
1565 uc->rchan->id); in udma_put_rchan()
1566 clear_bit(uc->rchan->id, ud->rchan_map); in udma_put_rchan()
1567 uc->rchan = NULL; in udma_put_rchan()
1573 struct udma_dev *ud = uc->ud; in udma_put_tchan()
1575 if (uc->tchan) { in udma_put_tchan()
1576 dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id, in udma_put_tchan()
1577 uc->tchan->id); in udma_put_tchan()
1578 clear_bit(uc->tchan->id, ud->tchan_map); in udma_put_tchan()
1580 if (uc->tchan->tflow_id >= 0) in udma_put_tchan()
1581 clear_bit(uc->tchan->tflow_id, ud->tflow_map); in udma_put_tchan()
1583 uc->tchan = NULL; in udma_put_tchan()
1589 struct udma_dev *ud = uc->ud; in udma_put_rflow()
1591 if (uc->rflow) { in udma_put_rflow()
1592 dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id, in udma_put_rflow()
1593 uc->rflow->id); in udma_put_rflow()
1594 __udma_put_rflow(ud, uc->rflow); in udma_put_rflow()
1595 uc->rflow = NULL; in udma_put_rflow()
1601 if (!uc->bchan) in bcdma_free_bchan_resources()
1604 k3_ringacc_ring_free(uc->bchan->tc_ring); in bcdma_free_bchan_resources()
1605 k3_ringacc_ring_free(uc->bchan->t_ring); in bcdma_free_bchan_resources()
1606 uc->bchan->tc_ring = NULL; in bcdma_free_bchan_resources()
1607 uc->bchan->t_ring = NULL; in bcdma_free_bchan_resources()
1608 k3_configure_chan_coherency(&uc->vc.chan, 0); in bcdma_free_bchan_resources()
1616 struct udma_dev *ud = uc->ud; in bcdma_alloc_bchan_resources()
1623 ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1, in bcdma_alloc_bchan_resources()
1624 &uc->bchan->t_ring, in bcdma_alloc_bchan_resources()
1625 &uc->bchan->tc_ring); in bcdma_alloc_bchan_resources()
1627 ret = -EBUSY; in bcdma_alloc_bchan_resources()
1636 k3_configure_chan_coherency(&uc->vc.chan, ud->asel); in bcdma_alloc_bchan_resources()
1637 ring_cfg.asel = ud->asel; in bcdma_alloc_bchan_resources()
1638 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); in bcdma_alloc_bchan_resources()
1640 ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg); in bcdma_alloc_bchan_resources()
1647 k3_ringacc_ring_free(uc->bchan->tc_ring); in bcdma_alloc_bchan_resources()
1648 uc->bchan->tc_ring = NULL; in bcdma_alloc_bchan_resources()
1649 k3_ringacc_ring_free(uc->bchan->t_ring); in bcdma_alloc_bchan_resources()
1650 uc->bchan->t_ring = NULL; in bcdma_alloc_bchan_resources()
1651 k3_configure_chan_coherency(&uc->vc.chan, 0); in bcdma_alloc_bchan_resources()
1660 if (!uc->tchan) in udma_free_tx_resources()
1663 k3_ringacc_ring_free(uc->tchan->t_ring); in udma_free_tx_resources()
1664 k3_ringacc_ring_free(uc->tchan->tc_ring); in udma_free_tx_resources()
1665 uc->tchan->t_ring = NULL; in udma_free_tx_resources()
1666 uc->tchan->tc_ring = NULL; in udma_free_tx_resources()
1674 struct udma_dev *ud = uc->ud; in udma_alloc_tx_resources()
1682 tchan = uc->tchan; in udma_alloc_tx_resources()
1683 if (tchan->tflow_id >= 0) in udma_alloc_tx_resources()
1684 ring_idx = tchan->tflow_id; in udma_alloc_tx_resources()
1686 ring_idx = ud->bchan_cnt + tchan->id; in udma_alloc_tx_resources()
1688 ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, in udma_alloc_tx_resources()
1689 &tchan->t_ring, in udma_alloc_tx_resources()
1690 &tchan->tc_ring); in udma_alloc_tx_resources()
1692 ret = -EBUSY; in udma_alloc_tx_resources()
1699 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_alloc_tx_resources()
1704 k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); in udma_alloc_tx_resources()
1705 ring_cfg.asel = uc->config.asel; in udma_alloc_tx_resources()
1706 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); in udma_alloc_tx_resources()
1709 ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg); in udma_alloc_tx_resources()
1710 ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg); in udma_alloc_tx_resources()
1718 k3_ringacc_ring_free(uc->tchan->tc_ring); in udma_alloc_tx_resources()
1719 uc->tchan->tc_ring = NULL; in udma_alloc_tx_resources()
1720 k3_ringacc_ring_free(uc->tchan->t_ring); in udma_alloc_tx_resources()
1721 uc->tchan->t_ring = NULL; in udma_alloc_tx_resources()
1730 if (!uc->rchan) in udma_free_rx_resources()
1733 if (uc->rflow) { in udma_free_rx_resources()
1734 struct udma_rflow *rflow = uc->rflow; in udma_free_rx_resources()
1736 k3_ringacc_ring_free(rflow->fd_ring); in udma_free_rx_resources()
1737 k3_ringacc_ring_free(rflow->r_ring); in udma_free_rx_resources()
1738 rflow->fd_ring = NULL; in udma_free_rx_resources()
1739 rflow->r_ring = NULL; in udma_free_rx_resources()
1749 struct udma_dev *ud = uc->ud; in udma_alloc_rx_resources()
1760 if (uc->config.dir == DMA_MEM_TO_MEM) in udma_alloc_rx_resources()
1763 if (uc->config.default_flow_id >= 0) in udma_alloc_rx_resources()
1764 ret = udma_get_rflow(uc, uc->config.default_flow_id); in udma_alloc_rx_resources()
1766 ret = udma_get_rflow(uc, uc->rchan->id); in udma_alloc_rx_resources()
1769 ret = -EBUSY; in udma_alloc_rx_resources()
1773 rflow = uc->rflow; in udma_alloc_rx_resources()
1774 if (ud->tflow_cnt) in udma_alloc_rx_resources()
1775 fd_ring_id = ud->tflow_cnt + rflow->id; in udma_alloc_rx_resources()
1777 fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt + in udma_alloc_rx_resources()
1778 uc->rchan->id; in udma_alloc_rx_resources()
1780 ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1, in udma_alloc_rx_resources()
1781 &rflow->fd_ring, &rflow->r_ring); in udma_alloc_rx_resources()
1783 ret = -EBUSY; in udma_alloc_rx_resources()
1790 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_alloc_rx_resources()
1791 if (uc->config.pkt_mode) in udma_alloc_rx_resources()
1801 k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel); in udma_alloc_rx_resources()
1802 ring_cfg.asel = uc->config.asel; in udma_alloc_rx_resources()
1803 ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan); in udma_alloc_rx_resources()
1806 ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg); in udma_alloc_rx_resources()
1809 ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg); in udma_alloc_rx_resources()
1817 k3_ringacc_ring_free(rflow->r_ring); in udma_alloc_rx_resources()
1818 rflow->r_ring = NULL; in udma_alloc_rx_resources()
1819 k3_ringacc_ring_free(rflow->fd_ring); in udma_alloc_rx_resources()
1820 rflow->fd_ring = NULL; in udma_alloc_rx_resources()
1863 struct udma_dev *ud = uc->ud; in udma_tisci_m2m_channel_config()
1864 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_tisci_m2m_channel_config()
1865 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in udma_tisci_m2m_channel_config()
1866 struct udma_tchan *tchan = uc->tchan; in udma_tisci_m2m_channel_config()
1867 struct udma_rchan *rchan = uc->rchan; in udma_tisci_m2m_channel_config() local
1872 /* Non synchronized - mem to mem type of transfer */ in udma_tisci_m2m_channel_config()
1873 int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring); in udma_tisci_m2m_channel_config()
1877 if (ud->match_data->flags & UDMA_FLAG_BURST_SIZE) { in udma_tisci_m2m_channel_config()
1878 tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, tchan->id); in udma_tisci_m2m_channel_config()
1880 burst_size = ud->match_data->burst_size[tpl]; in udma_tisci_m2m_channel_config()
1884 req_tx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_m2m_channel_config()
1885 req_tx.index = tchan->id; in udma_tisci_m2m_channel_config()
1889 req_tx.tx_atype = ud->atype; in udma_tisci_m2m_channel_config()
1895 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in udma_tisci_m2m_channel_config()
1897 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); in udma_tisci_m2m_channel_config()
1902 req_rx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_m2m_channel_config()
1903 req_rx.index = rchan->id; in udma_tisci_m2m_channel_config()
1907 req_rx.rx_atype = ud->atype; in udma_tisci_m2m_channel_config()
1913 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in udma_tisci_m2m_channel_config()
1915 dev_err(ud->dev, "rchan%d alloc failed %d\n", rchan->id, ret); in udma_tisci_m2m_channel_config()
1922 struct udma_dev *ud = uc->ud; in bcdma_tisci_m2m_channel_config()
1923 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_tisci_m2m_channel_config()
1924 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in bcdma_tisci_m2m_channel_config()
1926 struct udma_bchan *bchan = uc->bchan; in bcdma_tisci_m2m_channel_config()
1931 if (ud->match_data->flags & UDMA_FLAG_BURST_SIZE) { in bcdma_tisci_m2m_channel_config()
1932 tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, bchan->id); in bcdma_tisci_m2m_channel_config()
1934 burst_size = ud->match_data->burst_size[tpl]; in bcdma_tisci_m2m_channel_config()
1938 req_tx.nav_id = tisci_rm->tisci_dev_id; in bcdma_tisci_m2m_channel_config()
1940 req_tx.index = bchan->id; in bcdma_tisci_m2m_channel_config()
1946 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in bcdma_tisci_m2m_channel_config()
1948 dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret); in bcdma_tisci_m2m_channel_config()
1955 struct udma_dev *ud = uc->ud; in udma_tisci_tx_channel_config()
1956 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_tisci_tx_channel_config()
1957 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in udma_tisci_tx_channel_config()
1958 struct udma_tchan *tchan = uc->tchan; in udma_tisci_tx_channel_config()
1959 int tc_ring = k3_ringacc_get_ring_id(tchan->tc_ring); in udma_tisci_tx_channel_config()
1964 if (uc->config.pkt_mode) { in udma_tisci_tx_channel_config()
1966 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, in udma_tisci_tx_channel_config()
1967 uc->config.psd_size, 0); in udma_tisci_tx_channel_config()
1974 req_tx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_tx_channel_config()
1975 req_tx.index = tchan->id; in udma_tisci_tx_channel_config()
1977 req_tx.tx_supr_tdpkt = uc->config.notdpkt; in udma_tisci_tx_channel_config()
1980 req_tx.tx_atype = uc->config.atype; in udma_tisci_tx_channel_config()
1981 if (uc->config.ep_type == PSIL_EP_PDMA_XY && in udma_tisci_tx_channel_config()
1982 ud->match_data->flags & UDMA_FLAG_TDTYPE) { in udma_tisci_tx_channel_config()
1989 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in udma_tisci_tx_channel_config()
1991 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); in udma_tisci_tx_channel_config()
1998 struct udma_dev *ud = uc->ud; in bcdma_tisci_tx_channel_config()
1999 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_tisci_tx_channel_config()
2000 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in bcdma_tisci_tx_channel_config()
2001 struct udma_tchan *tchan = uc->tchan; in bcdma_tisci_tx_channel_config()
2006 req_tx.nav_id = tisci_rm->tisci_dev_id; in bcdma_tisci_tx_channel_config()
2007 req_tx.index = tchan->id; in bcdma_tisci_tx_channel_config()
2008 req_tx.tx_supr_tdpkt = uc->config.notdpkt; in bcdma_tisci_tx_channel_config()
2009 if (ud->match_data->flags & UDMA_FLAG_TDTYPE) { in bcdma_tisci_tx_channel_config()
2016 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx); in bcdma_tisci_tx_channel_config()
2018 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); in bcdma_tisci_tx_channel_config()
2027 struct udma_dev *ud = uc->ud; in udma_tisci_rx_channel_config()
2028 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_tisci_rx_channel_config()
2029 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in udma_tisci_rx_channel_config()
2030 struct udma_rchan *rchan = uc->rchan; in udma_tisci_rx_channel_config() local
2031 int fd_ring = k3_ringacc_get_ring_id(uc->rflow->fd_ring); in udma_tisci_rx_channel_config()
2032 int rx_ring = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_tisci_rx_channel_config()
2038 if (uc->config.pkt_mode) { in udma_tisci_rx_channel_config()
2040 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, in udma_tisci_rx_channel_config()
2041 uc->config.psd_size, 0); in udma_tisci_rx_channel_config()
2048 req_rx.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_rx_channel_config()
2049 req_rx.index = rchan->id; in udma_tisci_rx_channel_config()
2053 req_rx.rx_atype = uc->config.atype; in udma_tisci_rx_channel_config()
2055 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in udma_tisci_rx_channel_config()
2057 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret); in udma_tisci_rx_channel_config()
2076 flow_req.nav_id = tisci_rm->tisci_dev_id; in udma_tisci_rx_channel_config()
2077 flow_req.flow_index = rchan->id; in udma_tisci_rx_channel_config()
2079 if (uc->config.needs_epib) in udma_tisci_rx_channel_config()
2083 if (uc->config.psd_size) in udma_tisci_rx_channel_config()
2098 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); in udma_tisci_rx_channel_config()
2101 dev_err(ud->dev, "flow%d config failed: %d\n", rchan->id, ret); in udma_tisci_rx_channel_config()
2108 struct udma_dev *ud = uc->ud; in bcdma_tisci_rx_channel_config()
2109 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_tisci_rx_channel_config()
2110 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in bcdma_tisci_rx_channel_config()
2111 struct udma_rchan *rchan = uc->rchan; in bcdma_tisci_rx_channel_config() local
2116 req_rx.nav_id = tisci_rm->tisci_dev_id; in bcdma_tisci_rx_channel_config()
2117 req_rx.index = rchan->id; in bcdma_tisci_rx_channel_config()
2119 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in bcdma_tisci_rx_channel_config()
2121 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret); in bcdma_tisci_rx_channel_config()
2128 struct udma_dev *ud = uc->ud; in pktdma_tisci_rx_channel_config()
2129 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in pktdma_tisci_rx_channel_config()
2130 const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops; in pktdma_tisci_rx_channel_config()
2136 req_rx.nav_id = tisci_rm->tisci_dev_id; in pktdma_tisci_rx_channel_config()
2137 req_rx.index = uc->rchan->id; in pktdma_tisci_rx_channel_config()
2139 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx); in pktdma_tisci_rx_channel_config()
2141 dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret); in pktdma_tisci_rx_channel_config()
2150 flow_req.nav_id = tisci_rm->tisci_dev_id; in pktdma_tisci_rx_channel_config()
2151 flow_req.flow_index = uc->rflow->id; in pktdma_tisci_rx_channel_config()
2153 if (uc->config.needs_epib) in pktdma_tisci_rx_channel_config()
2157 if (uc->config.psd_size) in pktdma_tisci_rx_channel_config()
2163 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); in pktdma_tisci_rx_channel_config()
2166 dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id, in pktdma_tisci_rx_channel_config()
2175 struct udma_dev *ud = to_udma_dev(chan->device); in udma_alloc_chan_resources()
2176 const struct udma_soc_data *soc_data = ud->soc_data; in udma_alloc_chan_resources()
2181 uc->dma_dev = ud->dev; in udma_alloc_chan_resources()
2183 if (uc->config.pkt_mode || uc->config.dir == DMA_MEM_TO_MEM) { in udma_alloc_chan_resources()
2184 uc->use_dma_pool = true; in udma_alloc_chan_resources()
2186 if (uc->config.dir == DMA_MEM_TO_MEM) { in udma_alloc_chan_resources()
2187 uc->config.hdesc_size = cppi5_trdesc_calc_size( in udma_alloc_chan_resources()
2189 uc->config.pkt_mode = false; in udma_alloc_chan_resources()
2193 if (uc->use_dma_pool) { in udma_alloc_chan_resources()
2194 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev, in udma_alloc_chan_resources()
2195 uc->config.hdesc_size, in udma_alloc_chan_resources()
2196 ud->desc_align, in udma_alloc_chan_resources()
2198 if (!uc->hdesc_pool) { in udma_alloc_chan_resources()
2199 dev_err(ud->ddev.dev, in udma_alloc_chan_resources()
2201 uc->use_dma_pool = false; in udma_alloc_chan_resources()
2202 ret = -ENOMEM; in udma_alloc_chan_resources()
2211 reinit_completion(&uc->teardown_completed); in udma_alloc_chan_resources()
2212 complete_all(&uc->teardown_completed); in udma_alloc_chan_resources()
2213 uc->state = UDMA_CHAN_IS_IDLE; in udma_alloc_chan_resources()
2215 switch (uc->config.dir) { in udma_alloc_chan_resources()
2217 /* Non synchronized - mem to mem type of transfer */ in udma_alloc_chan_resources()
2218 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__, in udma_alloc_chan_resources()
2219 uc->id); in udma_alloc_chan_resources()
2237 uc->config.src_thread = ud->psil_base + uc->tchan->id; in udma_alloc_chan_resources()
2238 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in udma_alloc_chan_resources()
2241 irq_ring = uc->tchan->tc_ring; in udma_alloc_chan_resources()
2242 irq_udma_idx = uc->tchan->id; in udma_alloc_chan_resources()
2247 /* Slave transfer synchronized - mem to dev (TX) trasnfer */ in udma_alloc_chan_resources()
2248 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, in udma_alloc_chan_resources()
2249 uc->id); in udma_alloc_chan_resources()
2255 uc->config.src_thread = ud->psil_base + uc->tchan->id; in udma_alloc_chan_resources()
2256 uc->config.dst_thread = uc->config.remote_thread_id; in udma_alloc_chan_resources()
2257 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; in udma_alloc_chan_resources()
2259 irq_ring = uc->tchan->tc_ring; in udma_alloc_chan_resources()
2260 irq_udma_idx = uc->tchan->id; in udma_alloc_chan_resources()
2265 /* Slave transfer synchronized - dev to mem (RX) trasnfer */ in udma_alloc_chan_resources()
2266 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, in udma_alloc_chan_resources()
2267 uc->id); in udma_alloc_chan_resources()
2273 uc->config.src_thread = uc->config.remote_thread_id; in udma_alloc_chan_resources()
2274 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in udma_alloc_chan_resources()
2277 irq_ring = uc->rflow->r_ring; in udma_alloc_chan_resources()
2278 irq_udma_idx = soc_data->oes.udma_rchan + uc->rchan->id; in udma_alloc_chan_resources()
2284 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", in udma_alloc_chan_resources()
2285 __func__, uc->id, uc->config.dir); in udma_alloc_chan_resources()
2286 ret = -EINVAL; in udma_alloc_chan_resources()
2296 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); in udma_alloc_chan_resources()
2299 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); in udma_alloc_chan_resources()
2300 ret = -EBUSY; in udma_alloc_chan_resources()
2305 /* PSI-L pairing */ in udma_alloc_chan_resources()
2306 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); in udma_alloc_chan_resources()
2308 dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", in udma_alloc_chan_resources()
2309 uc->config.src_thread, uc->config.dst_thread); in udma_alloc_chan_resources()
2313 uc->psil_paired = true; in udma_alloc_chan_resources()
2315 uc->irq_num_ring = k3_ringacc_get_ring_irq_num(irq_ring); in udma_alloc_chan_resources()
2316 if (uc->irq_num_ring <= 0) { in udma_alloc_chan_resources()
2317 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n", in udma_alloc_chan_resources()
2319 ret = -EINVAL; in udma_alloc_chan_resources()
2323 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, in udma_alloc_chan_resources()
2324 IRQF_TRIGGER_HIGH, uc->name, uc); in udma_alloc_chan_resources()
2326 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); in udma_alloc_chan_resources()
2331 if (is_slave_direction(uc->config.dir) && !uc->config.pkt_mode) { in udma_alloc_chan_resources()
2332 uc->irq_num_udma = msi_get_virq(ud->dev, irq_udma_idx); in udma_alloc_chan_resources()
2333 if (uc->irq_num_udma <= 0) { in udma_alloc_chan_resources()
2334 dev_err(ud->dev, "Failed to get udma irq (index: %u)\n", in udma_alloc_chan_resources()
2336 free_irq(uc->irq_num_ring, uc); in udma_alloc_chan_resources()
2337 ret = -EINVAL; in udma_alloc_chan_resources()
2341 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0, in udma_alloc_chan_resources()
2342 uc->name, uc); in udma_alloc_chan_resources()
2344 dev_err(ud->dev, "chan%d: UDMA irq request failed\n", in udma_alloc_chan_resources()
2345 uc->id); in udma_alloc_chan_resources()
2346 free_irq(uc->irq_num_ring, uc); in udma_alloc_chan_resources()
2350 uc->irq_num_udma = 0; in udma_alloc_chan_resources()
2358 uc->irq_num_ring = 0; in udma_alloc_chan_resources()
2359 uc->irq_num_udma = 0; in udma_alloc_chan_resources()
2361 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); in udma_alloc_chan_resources()
2362 uc->psil_paired = false; in udma_alloc_chan_resources()
2369 if (uc->use_dma_pool) { in udma_alloc_chan_resources()
2370 dma_pool_destroy(uc->hdesc_pool); in udma_alloc_chan_resources()
2371 uc->use_dma_pool = false; in udma_alloc_chan_resources()
2380 struct udma_dev *ud = to_udma_dev(chan->device); in bcdma_alloc_chan_resources()
2381 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in bcdma_alloc_chan_resources()
2386 uc->config.pkt_mode = false; in bcdma_alloc_chan_resources()
2392 reinit_completion(&uc->teardown_completed); in bcdma_alloc_chan_resources()
2393 complete_all(&uc->teardown_completed); in bcdma_alloc_chan_resources()
2394 uc->state = UDMA_CHAN_IS_IDLE; in bcdma_alloc_chan_resources()
2396 switch (uc->config.dir) { in bcdma_alloc_chan_resources()
2398 /* Non synchronized - mem to mem type of transfer */ in bcdma_alloc_chan_resources()
2399 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__, in bcdma_alloc_chan_resources()
2400 uc->id); in bcdma_alloc_chan_resources()
2406 irq_ring_idx = uc->bchan->id + oes->bcdma_bchan_ring; in bcdma_alloc_chan_resources()
2407 irq_udma_idx = uc->bchan->id + oes->bcdma_bchan_data; in bcdma_alloc_chan_resources()
2412 /* Slave transfer synchronized - mem to dev (TX) trasnfer */ in bcdma_alloc_chan_resources()
2413 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, in bcdma_alloc_chan_resources()
2414 uc->id); in bcdma_alloc_chan_resources()
2418 uc->config.remote_thread_id = -1; in bcdma_alloc_chan_resources()
2422 uc->config.src_thread = ud->psil_base + uc->tchan->id; in bcdma_alloc_chan_resources()
2423 uc->config.dst_thread = uc->config.remote_thread_id; in bcdma_alloc_chan_resources()
2424 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; in bcdma_alloc_chan_resources()
2426 irq_ring_idx = uc->tchan->id + oes->bcdma_tchan_ring; in bcdma_alloc_chan_resources()
2427 irq_udma_idx = uc->tchan->id + oes->bcdma_tchan_data; in bcdma_alloc_chan_resources()
2432 /* Slave transfer synchronized - dev to mem (RX) trasnfer */ in bcdma_alloc_chan_resources()
2433 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, in bcdma_alloc_chan_resources()
2434 uc->id); in bcdma_alloc_chan_resources()
2438 uc->config.remote_thread_id = -1; in bcdma_alloc_chan_resources()
2442 uc->config.src_thread = uc->config.remote_thread_id; in bcdma_alloc_chan_resources()
2443 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in bcdma_alloc_chan_resources()
2446 irq_ring_idx = uc->rchan->id + oes->bcdma_rchan_ring; in bcdma_alloc_chan_resources()
2447 irq_udma_idx = uc->rchan->id + oes->bcdma_rchan_data; in bcdma_alloc_chan_resources()
2453 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", in bcdma_alloc_chan_resources()
2454 __func__, uc->id, uc->config.dir); in bcdma_alloc_chan_resources()
2455 return -EINVAL; in bcdma_alloc_chan_resources()
2463 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); in bcdma_alloc_chan_resources()
2466 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); in bcdma_alloc_chan_resources()
2467 ret = -EBUSY; in bcdma_alloc_chan_resources()
2472 uc->dma_dev = dmaengine_get_dma_device(chan); in bcdma_alloc_chan_resources()
2473 if (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type) { in bcdma_alloc_chan_resources()
2474 uc->config.hdesc_size = cppi5_trdesc_calc_size( in bcdma_alloc_chan_resources()
2477 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev, in bcdma_alloc_chan_resources()
2478 uc->config.hdesc_size, in bcdma_alloc_chan_resources()
2479 ud->desc_align, in bcdma_alloc_chan_resources()
2481 if (!uc->hdesc_pool) { in bcdma_alloc_chan_resources()
2482 dev_err(ud->ddev.dev, in bcdma_alloc_chan_resources()
2484 uc->use_dma_pool = false; in bcdma_alloc_chan_resources()
2485 ret = -ENOMEM; in bcdma_alloc_chan_resources()
2489 uc->use_dma_pool = true; in bcdma_alloc_chan_resources()
2490 } else if (uc->config.dir != DMA_MEM_TO_MEM) { in bcdma_alloc_chan_resources()
2491 /* PSI-L pairing */ in bcdma_alloc_chan_resources()
2492 ret = navss_psil_pair(ud, uc->config.src_thread, in bcdma_alloc_chan_resources()
2493 uc->config.dst_thread); in bcdma_alloc_chan_resources()
2495 dev_err(ud->dev, in bcdma_alloc_chan_resources()
2496 "PSI-L pairing failed: 0x%04x -> 0x%04x\n", in bcdma_alloc_chan_resources()
2497 uc->config.src_thread, uc->config.dst_thread); in bcdma_alloc_chan_resources()
2501 uc->psil_paired = true; in bcdma_alloc_chan_resources()
2504 uc->irq_num_ring = msi_get_virq(ud->dev, irq_ring_idx); in bcdma_alloc_chan_resources()
2505 if (uc->irq_num_ring <= 0) { in bcdma_alloc_chan_resources()
2506 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n", in bcdma_alloc_chan_resources()
2508 ret = -EINVAL; in bcdma_alloc_chan_resources()
2512 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, in bcdma_alloc_chan_resources()
2513 IRQF_TRIGGER_HIGH, uc->name, uc); in bcdma_alloc_chan_resources()
2515 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); in bcdma_alloc_chan_resources()
2520 if (is_slave_direction(uc->config.dir)) { in bcdma_alloc_chan_resources()
2521 uc->irq_num_udma = msi_get_virq(ud->dev, irq_udma_idx); in bcdma_alloc_chan_resources()
2522 if (uc->irq_num_udma <= 0) { in bcdma_alloc_chan_resources()
2523 dev_err(ud->dev, "Failed to get bcdma irq (index: %u)\n", in bcdma_alloc_chan_resources()
2525 free_irq(uc->irq_num_ring, uc); in bcdma_alloc_chan_resources()
2526 ret = -EINVAL; in bcdma_alloc_chan_resources()
2530 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0, in bcdma_alloc_chan_resources()
2531 uc->name, uc); in bcdma_alloc_chan_resources()
2533 dev_err(ud->dev, "chan%d: BCDMA irq request failed\n", in bcdma_alloc_chan_resources()
2534 uc->id); in bcdma_alloc_chan_resources()
2535 free_irq(uc->irq_num_ring, uc); in bcdma_alloc_chan_resources()
2539 uc->irq_num_udma = 0; in bcdma_alloc_chan_resources()
2544 INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, in bcdma_alloc_chan_resources()
2549 uc->irq_num_ring = 0; in bcdma_alloc_chan_resources()
2550 uc->irq_num_udma = 0; in bcdma_alloc_chan_resources()
2552 if (uc->psil_paired) in bcdma_alloc_chan_resources()
2553 navss_psil_unpair(ud, uc->config.src_thread, in bcdma_alloc_chan_resources()
2554 uc->config.dst_thread); in bcdma_alloc_chan_resources()
2555 uc->psil_paired = false; in bcdma_alloc_chan_resources()
2563 if (uc->use_dma_pool) { in bcdma_alloc_chan_resources()
2564 dma_pool_destroy(uc->hdesc_pool); in bcdma_alloc_chan_resources()
2565 uc->use_dma_pool = false; in bcdma_alloc_chan_resources()
2573 struct k3_event_route_data *router_data = chan->route_data; in bcdma_router_config()
2577 if (!uc->bchan) in bcdma_router_config()
2578 return -EINVAL; in bcdma_router_config()
2580 if (uc->config.tr_trigger_type != 1 && uc->config.tr_trigger_type != 2) in bcdma_router_config()
2581 return -EINVAL; in bcdma_router_config()
2583 trigger_event = uc->ud->soc_data->bcdma_trigger_event_offset; in bcdma_router_config()
2584 trigger_event += (uc->bchan->id * 2) + uc->config.tr_trigger_type - 1; in bcdma_router_config()
2586 return router_data->set_event(router_data->priv, trigger_event); in bcdma_router_config()
2592 struct udma_dev *ud = to_udma_dev(chan->device); in pktdma_alloc_chan_resources()
2593 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in pktdma_alloc_chan_resources()
2601 reinit_completion(&uc->teardown_completed); in pktdma_alloc_chan_resources()
2602 complete_all(&uc->teardown_completed); in pktdma_alloc_chan_resources()
2603 uc->state = UDMA_CHAN_IS_IDLE; in pktdma_alloc_chan_resources()
2605 switch (uc->config.dir) { in pktdma_alloc_chan_resources()
2607 /* Slave transfer synchronized - mem to dev (TX) trasnfer */ in pktdma_alloc_chan_resources()
2608 dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, in pktdma_alloc_chan_resources()
2609 uc->id); in pktdma_alloc_chan_resources()
2613 uc->config.remote_thread_id = -1; in pktdma_alloc_chan_resources()
2617 uc->config.src_thread = ud->psil_base + uc->tchan->id; in pktdma_alloc_chan_resources()
2618 uc->config.dst_thread = uc->config.remote_thread_id; in pktdma_alloc_chan_resources()
2619 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET; in pktdma_alloc_chan_resources()
2621 irq_ring_idx = uc->tchan->tflow_id + oes->pktdma_tchan_flow; in pktdma_alloc_chan_resources()
2626 /* Slave transfer synchronized - dev to mem (RX) trasnfer */ in pktdma_alloc_chan_resources()
2627 dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, in pktdma_alloc_chan_resources()
2628 uc->id); in pktdma_alloc_chan_resources()
2632 uc->config.remote_thread_id = -1; in pktdma_alloc_chan_resources()
2636 uc->config.src_thread = uc->config.remote_thread_id; in pktdma_alloc_chan_resources()
2637 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | in pktdma_alloc_chan_resources()
2640 irq_ring_idx = uc->rflow->id + oes->pktdma_rchan_flow; in pktdma_alloc_chan_resources()
2646 dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", in pktdma_alloc_chan_resources()
2647 __func__, uc->id, uc->config.dir); in pktdma_alloc_chan_resources()
2648 return -EINVAL; in pktdma_alloc_chan_resources()
2656 dev_warn(ud->dev, "chan%d: is running!\n", uc->id); in pktdma_alloc_chan_resources()
2659 dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); in pktdma_alloc_chan_resources()
2660 ret = -EBUSY; in pktdma_alloc_chan_resources()
2665 uc->dma_dev = dmaengine_get_dma_device(chan); in pktdma_alloc_chan_resources()
2666 uc->hdesc_pool = dma_pool_create(uc->name, uc->dma_dev, in pktdma_alloc_chan_resources()
2667 uc->config.hdesc_size, ud->desc_align, in pktdma_alloc_chan_resources()
2669 if (!uc->hdesc_pool) { in pktdma_alloc_chan_resources()
2670 dev_err(ud->ddev.dev, in pktdma_alloc_chan_resources()
2672 uc->use_dma_pool = false; in pktdma_alloc_chan_resources()
2673 ret = -ENOMEM; in pktdma_alloc_chan_resources()
2677 uc->use_dma_pool = true; in pktdma_alloc_chan_resources()
2679 /* PSI-L pairing */ in pktdma_alloc_chan_resources()
2680 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread); in pktdma_alloc_chan_resources()
2682 dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n", in pktdma_alloc_chan_resources()
2683 uc->config.src_thread, uc->config.dst_thread); in pktdma_alloc_chan_resources()
2687 uc->psil_paired = true; in pktdma_alloc_chan_resources()
2689 uc->irq_num_ring = msi_get_virq(ud->dev, irq_ring_idx); in pktdma_alloc_chan_resources()
2690 if (uc->irq_num_ring <= 0) { in pktdma_alloc_chan_resources()
2691 dev_err(ud->dev, "Failed to get ring irq (index: %u)\n", in pktdma_alloc_chan_resources()
2693 ret = -EINVAL; in pktdma_alloc_chan_resources()
2697 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler, in pktdma_alloc_chan_resources()
2698 IRQF_TRIGGER_HIGH, uc->name, uc); in pktdma_alloc_chan_resources()
2700 dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); in pktdma_alloc_chan_resources()
2704 uc->irq_num_udma = 0; in pktdma_alloc_chan_resources()
2708 INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, in pktdma_alloc_chan_resources()
2711 if (uc->tchan) in pktdma_alloc_chan_resources()
2712 dev_dbg(ud->dev, in pktdma_alloc_chan_resources()
2714 uc->id, uc->tchan->id, uc->tchan->tflow_id, in pktdma_alloc_chan_resources()
2715 uc->config.remote_thread_id); in pktdma_alloc_chan_resources()
2716 else if (uc->rchan) in pktdma_alloc_chan_resources()
2717 dev_dbg(ud->dev, in pktdma_alloc_chan_resources()
2718 "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n", in pktdma_alloc_chan_resources()
2719 uc->id, uc->rchan->id, uc->rflow->id, in pktdma_alloc_chan_resources()
2720 uc->config.remote_thread_id); in pktdma_alloc_chan_resources()
2724 uc->irq_num_ring = 0; in pktdma_alloc_chan_resources()
2726 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread); in pktdma_alloc_chan_resources()
2727 uc->psil_paired = false; in pktdma_alloc_chan_resources()
2734 dma_pool_destroy(uc->hdesc_pool); in pktdma_alloc_chan_resources()
2735 uc->use_dma_pool = false; in pktdma_alloc_chan_resources()
2745 memcpy(&uc->cfg, cfg, sizeof(uc->cfg)); in udma_slave_config()
2767 dev_err(uc->ud->dev, "Unsupported TR size of %zu\n", tr_size); in udma_alloc_tr_desc()
2772 d = kzalloc(sizeof(*d) + sizeof(d->hwdesc[0]), GFP_NOWAIT); in udma_alloc_tr_desc()
2776 d->sglen = tr_count; in udma_alloc_tr_desc()
2778 d->hwdesc_count = 1; in udma_alloc_tr_desc()
2779 hwdesc = &d->hwdesc[0]; in udma_alloc_tr_desc()
2782 if (uc->use_dma_pool) { in udma_alloc_tr_desc()
2783 hwdesc->cppi5_desc_size = uc->config.hdesc_size; in udma_alloc_tr_desc()
2784 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, in udma_alloc_tr_desc()
2786 &hwdesc->cppi5_desc_paddr); in udma_alloc_tr_desc()
2788 hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, in udma_alloc_tr_desc()
2790 hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, in udma_alloc_tr_desc()
2791 uc->ud->desc_align); in udma_alloc_tr_desc()
2792 hwdesc->cppi5_desc_vaddr = dma_alloc_coherent(uc->ud->dev, in udma_alloc_tr_desc()
2793 hwdesc->cppi5_desc_size, in udma_alloc_tr_desc()
2794 &hwdesc->cppi5_desc_paddr, in udma_alloc_tr_desc()
2798 if (!hwdesc->cppi5_desc_vaddr) { in udma_alloc_tr_desc()
2804 hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; in udma_alloc_tr_desc()
2806 hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size * tr_count; in udma_alloc_tr_desc()
2808 tr_desc = hwdesc->cppi5_desc_vaddr; in udma_alloc_tr_desc()
2810 if (uc->cyclic) in udma_alloc_tr_desc()
2814 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_alloc_tr_desc()
2816 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); in udma_alloc_tr_desc()
2819 cppi5_desc_set_pktids(tr_desc, uc->id, in udma_alloc_tr_desc()
2827 * udma_get_tr_counters - calculate TR counters for a given length
2836 * First TR: SZ_64K-alignment blocks (tr0_cnt0, tr0_cnt1)
2840 * -EINVAL if the length can not be supported
2856 *tr0_cnt0 = SZ_64K - BIT(align_to); in udma_get_tr_counters()
2859 align_to--; in udma_get_tr_counters()
2862 return -EINVAL; in udma_get_tr_counters()
2900 d->sglen = sglen; in udma_prep_slave_sg_tr()
2902 if (uc->ud->match_data->type == DMA_TYPE_UDMA) in udma_prep_slave_sg_tr()
2905 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_slave_sg_tr()
2907 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_tr()
2914 dev_err(uc->ud->dev, "size %u is not supported\n", in udma_prep_slave_sg_tr()
2946 d->residue += sg_dma_len(sgent); in udma_prep_slave_sg_tr()
2949 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_tr()
2975 dev_addr = uc->cfg.src_addr; in udma_prep_slave_sg_triggered_tr()
2976 dev_width = uc->cfg.src_addr_width; in udma_prep_slave_sg_triggered_tr()
2977 burst = uc->cfg.src_maxburst; in udma_prep_slave_sg_triggered_tr()
2978 port_window = uc->cfg.src_port_window_size; in udma_prep_slave_sg_triggered_tr()
2980 dev_addr = uc->cfg.dst_addr; in udma_prep_slave_sg_triggered_tr()
2981 dev_width = uc->cfg.dst_addr_width; in udma_prep_slave_sg_triggered_tr()
2982 burst = uc->cfg.dst_maxburst; in udma_prep_slave_sg_triggered_tr()
2983 port_window = uc->cfg.dst_port_window_size; in udma_prep_slave_sg_triggered_tr()
2985 dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); in udma_prep_slave_sg_triggered_tr()
2994 dev_err(uc->ud->dev, in udma_prep_slave_sg_triggered_tr()
3012 dev_err(uc->ud->dev, in udma_prep_slave_sg_triggered_tr()
3030 d->sglen = sglen; in udma_prep_slave_sg_triggered_tr()
3032 if (uc->ud->match_data->type == DMA_TYPE_UDMA) { in udma_prep_slave_sg_triggered_tr()
3035 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_slave_sg_triggered_tr()
3039 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_slave_sg_triggered_tr()
3048 dev_err(uc->ud->dev, "size %zu is not supported\n", in udma_prep_slave_sg_triggered_tr()
3059 uc->config.tr_trigger_type, in udma_prep_slave_sg_triggered_tr()
3069 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3094 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3106 uc->config.tr_trigger_type, in udma_prep_slave_sg_triggered_tr()
3117 tr_req[tr_idx].dim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3140 tr_req[tr_idx].ddim1 = (-1) * tr_cnt0; in udma_prep_slave_sg_triggered_tr()
3145 d->residue += sg_len; in udma_prep_slave_sg_triggered_tr()
3148 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags, in udma_prep_slave_sg_triggered_tr()
3158 if (uc->config.ep_type != PSIL_EP_PDMA_XY) in udma_configure_statictr()
3164 d->static_tr.elsize = 0; in udma_configure_statictr()
3167 d->static_tr.elsize = 1; in udma_configure_statictr()
3170 d->static_tr.elsize = 2; in udma_configure_statictr()
3173 d->static_tr.elsize = 3; in udma_configure_statictr()
3176 d->static_tr.elsize = 4; in udma_configure_statictr()
3179 return -EINVAL; in udma_configure_statictr()
3182 d->static_tr.elcnt = elcnt; in udma_configure_statictr()
3190 if (uc->config.pkt_mode || !uc->cyclic) { in udma_configure_statictr()
3193 if (uc->cyclic) in udma_configure_statictr()
3194 d->static_tr.bstcnt = d->residue / d->sglen / div; in udma_configure_statictr()
3196 d->static_tr.bstcnt = d->residue / div; in udma_configure_statictr()
3198 if (uc->config.dir == DMA_DEV_TO_MEM && in udma_configure_statictr()
3199 d->static_tr.bstcnt > uc->ud->match_data->statictr_z_mask) in udma_configure_statictr()
3200 return -EINVAL; in udma_configure_statictr()
3202 d->static_tr.bstcnt = 0; in udma_configure_statictr()
3224 d->sglen = sglen; in udma_prep_slave_sg_pkt()
3225 d->hwdesc_count = sglen; in udma_prep_slave_sg_pkt()
3228 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_prep_slave_sg_pkt()
3230 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); in udma_prep_slave_sg_pkt()
3232 if (uc->ud->match_data->type == DMA_TYPE_UDMA) in udma_prep_slave_sg_pkt()
3235 asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_slave_sg_pkt()
3238 struct udma_hwdesc *hwdesc = &d->hwdesc[i]; in udma_prep_slave_sg_pkt()
3243 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, in udma_prep_slave_sg_pkt()
3245 &hwdesc->cppi5_desc_paddr); in udma_prep_slave_sg_pkt()
3246 if (!hwdesc->cppi5_desc_vaddr) { in udma_prep_slave_sg_pkt()
3247 dev_err(uc->ud->dev, in udma_prep_slave_sg_pkt()
3255 d->residue += sg_len; in udma_prep_slave_sg_pkt()
3256 hwdesc->cppi5_desc_size = uc->config.hdesc_size; in udma_prep_slave_sg_pkt()
3257 desc = hwdesc->cppi5_desc_vaddr; in udma_prep_slave_sg_pkt()
3262 cppi5_desc_set_pktids(&desc->hdr, uc->id, in udma_prep_slave_sg_pkt()
3264 cppi5_desc_set_retpolicy(&desc->hdr, 0, ring_id); in udma_prep_slave_sg_pkt()
3267 cppi5_desc_set_retpolicy(&desc->hdr, 0, 0xffff); in udma_prep_slave_sg_pkt()
3277 hwdesc->cppi5_desc_paddr | asel); in udma_prep_slave_sg_pkt()
3279 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA || in udma_prep_slave_sg_pkt()
3284 if (d->residue >= SZ_4M) { in udma_prep_slave_sg_pkt()
3285 dev_err(uc->ud->dev, in udma_prep_slave_sg_pkt()
3286 "%s: Transfer size %u is over the supported 4M range\n", in udma_prep_slave_sg_pkt()
3287 __func__, d->residue); in udma_prep_slave_sg_pkt()
3293 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_prep_slave_sg_pkt()
3294 cppi5_hdesc_set_pktlen(h_desc, d->residue); in udma_prep_slave_sg_pkt()
3303 struct udma_chan *uc = to_udma_chan(desc->chan); in udma_attach_metadata()
3308 if (!uc->config.pkt_mode || !uc->config.metadata_size) in udma_attach_metadata()
3309 return -ENOTSUPP; in udma_attach_metadata()
3311 if (!data || len > uc->config.metadata_size) in udma_attach_metadata()
3312 return -EINVAL; in udma_attach_metadata()
3314 if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE) in udma_attach_metadata()
3315 return -EINVAL; in udma_attach_metadata()
3317 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_attach_metadata()
3318 if (d->dir == DMA_MEM_TO_DEV) in udma_attach_metadata()
3319 memcpy(h_desc->epib, data, len); in udma_attach_metadata()
3321 if (uc->config.needs_epib) in udma_attach_metadata()
3322 psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; in udma_attach_metadata()
3324 d->metadata = data; in udma_attach_metadata()
3325 d->metadata_size = len; in udma_attach_metadata()
3326 if (uc->config.needs_epib) in udma_attach_metadata()
3339 struct udma_chan *uc = to_udma_chan(desc->chan); in udma_get_metadata_ptr()
3342 if (!uc->config.pkt_mode || !uc->config.metadata_size) in udma_get_metadata_ptr()
3343 return ERR_PTR(-ENOTSUPP); in udma_get_metadata_ptr()
3345 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_get_metadata_ptr()
3347 *max_len = uc->config.metadata_size; in udma_get_metadata_ptr()
3349 *payload_len = cppi5_hdesc_epib_present(&h_desc->hdr) ? in udma_get_metadata_ptr()
3353 return h_desc->epib; in udma_get_metadata_ptr()
3360 struct udma_chan *uc = to_udma_chan(desc->chan); in udma_set_metadata_len()
3365 if (!uc->config.pkt_mode || !uc->config.metadata_size) in udma_set_metadata_len()
3366 return -ENOTSUPP; in udma_set_metadata_len()
3368 if (payload_len > uc->config.metadata_size) in udma_set_metadata_len()
3369 return -EINVAL; in udma_set_metadata_len()
3371 if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE) in udma_set_metadata_len()
3372 return -EINVAL; in udma_set_metadata_len()
3374 h_desc = d->hwdesc[0].cppi5_desc_vaddr; in udma_set_metadata_len()
3376 if (uc->config.needs_epib) { in udma_set_metadata_len()
3377 psd_size -= CPPI5_INFO0_HDESC_EPIB_SIZE; in udma_set_metadata_len()
3403 if (dir != uc->config.dir && in udma_prep_slave_sg()
3404 (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type)) { in udma_prep_slave_sg()
3405 dev_err(chan->device->dev, in udma_prep_slave_sg()
3407 __func__, uc->id, in udma_prep_slave_sg()
3408 dmaengine_get_direction_text(uc->config.dir), in udma_prep_slave_sg()
3414 dev_width = uc->cfg.src_addr_width; in udma_prep_slave_sg()
3415 burst = uc->cfg.src_maxburst; in udma_prep_slave_sg()
3417 dev_width = uc->cfg.dst_addr_width; in udma_prep_slave_sg()
3418 burst = uc->cfg.dst_maxburst; in udma_prep_slave_sg()
3420 dev_err(chan->device->dev, "%s: bad direction?\n", __func__); in udma_prep_slave_sg()
3427 uc->config.tx_flags = tx_flags; in udma_prep_slave_sg()
3429 if (uc->config.pkt_mode) in udma_prep_slave_sg()
3432 else if (is_slave_direction(uc->config.dir)) in udma_prep_slave_sg()
3442 d->dir = dir; in udma_prep_slave_sg()
3443 d->desc_idx = 0; in udma_prep_slave_sg()
3444 d->tr_idx = 0; in udma_prep_slave_sg()
3448 dev_err(uc->ud->dev, in udma_prep_slave_sg()
3450 __func__, d->static_tr.bstcnt); in udma_prep_slave_sg()
3457 if (uc->config.metadata_size) in udma_prep_slave_sg()
3458 d->vd.tx.metadata_ops = &metadata_ops; in udma_prep_slave_sg()
3460 return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); in udma_prep_slave_sg()
3479 dev_err(uc->ud->dev, "size %zu is not supported\n", in udma_prep_dma_cyclic_tr()
3490 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_cyclic_tr()
3491 if (uc->ud->match_data->type == DMA_TYPE_UDMA) in udma_prep_dma_cyclic_tr()
3495 ((u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT); in udma_prep_dma_cyclic_tr()
3543 if (periods > (K3_UDMA_DEFAULT_RING_SIZE - 1)) in udma_prep_dma_cyclic_pkt()
3553 d->hwdesc_count = periods; in udma_prep_dma_cyclic_pkt()
3555 /* TODO: re-check this... */ in udma_prep_dma_cyclic_pkt()
3557 ring_id = k3_ringacc_get_ring_id(uc->rflow->r_ring); in udma_prep_dma_cyclic_pkt()
3559 ring_id = k3_ringacc_get_ring_id(uc->tchan->tc_ring); in udma_prep_dma_cyclic_pkt()
3561 if (uc->ud->match_data->type != DMA_TYPE_UDMA) in udma_prep_dma_cyclic_pkt()
3562 buf_addr |= (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_dma_cyclic_pkt()
3565 struct udma_hwdesc *hwdesc = &d->hwdesc[i]; in udma_prep_dma_cyclic_pkt()
3569 hwdesc->cppi5_desc_vaddr = dma_pool_zalloc(uc->hdesc_pool, in udma_prep_dma_cyclic_pkt()
3571 &hwdesc->cppi5_desc_paddr); in udma_prep_dma_cyclic_pkt()
3572 if (!hwdesc->cppi5_desc_vaddr) { in udma_prep_dma_cyclic_pkt()
3573 dev_err(uc->ud->dev, in udma_prep_dma_cyclic_pkt()
3581 hwdesc->cppi5_desc_size = uc->config.hdesc_size; in udma_prep_dma_cyclic_pkt()
3582 h_desc = hwdesc->cppi5_desc_vaddr; in udma_prep_dma_cyclic_pkt()
3588 cppi5_desc_set_pktids(&h_desc->hdr, uc->id, in udma_prep_dma_cyclic_pkt()
3590 cppi5_desc_set_retpolicy(&h_desc->hdr, 0, ring_id); in udma_prep_dma_cyclic_pkt()
3611 if (dir != uc->config.dir) { in udma_prep_dma_cyclic()
3612 dev_err(chan->device->dev, in udma_prep_dma_cyclic()
3614 __func__, uc->id, in udma_prep_dma_cyclic()
3615 dmaengine_get_direction_text(uc->config.dir), in udma_prep_dma_cyclic()
3620 uc->cyclic = true; in udma_prep_dma_cyclic()
3623 dev_width = uc->cfg.src_addr_width; in udma_prep_dma_cyclic()
3624 burst = uc->cfg.src_maxburst; in udma_prep_dma_cyclic()
3626 dev_width = uc->cfg.dst_addr_width; in udma_prep_dma_cyclic()
3627 burst = uc->cfg.dst_maxburst; in udma_prep_dma_cyclic()
3629 dev_err(uc->ud->dev, "%s: bad direction?\n", __func__); in udma_prep_dma_cyclic()
3636 if (uc->config.pkt_mode) in udma_prep_dma_cyclic()
3646 d->sglen = buf_len / period_len; in udma_prep_dma_cyclic()
3648 d->dir = dir; in udma_prep_dma_cyclic()
3649 d->residue = buf_len; in udma_prep_dma_cyclic()
3653 dev_err(uc->ud->dev, in udma_prep_dma_cyclic()
3655 __func__, d->static_tr.bstcnt); in udma_prep_dma_cyclic()
3662 if (uc->config.metadata_size) in udma_prep_dma_cyclic()
3663 d->vd.tx.metadata_ops = &metadata_ops; in udma_prep_dma_cyclic()
3665 return vchan_tx_prep(&uc->vc, &d->vd, flags); in udma_prep_dma_cyclic()
3679 if (uc->config.dir != DMA_MEM_TO_MEM) { in udma_prep_dma_memcpy()
3680 dev_err(chan->device->dev, in udma_prep_dma_memcpy()
3682 __func__, uc->id, in udma_prep_dma_memcpy()
3683 dmaengine_get_direction_text(uc->config.dir), in udma_prep_dma_memcpy()
3691 dev_err(uc->ud->dev, "size %zu is not supported\n", in udma_prep_dma_memcpy()
3700 d->dir = DMA_MEM_TO_MEM; in udma_prep_dma_memcpy()
3701 d->desc_idx = 0; in udma_prep_dma_memcpy()
3702 d->tr_idx = 0; in udma_prep_dma_memcpy()
3703 d->residue = len; in udma_prep_dma_memcpy()
3705 if (uc->ud->match_data->type != DMA_TYPE_UDMA) { in udma_prep_dma_memcpy()
3706 src |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_dma_memcpy()
3707 dest |= (u64)uc->ud->asel << K3_ADDRESS_ASEL_SHIFT; in udma_prep_dma_memcpy()
3710 tr_req = d->hwdesc[0].tr_req_base; in udma_prep_dma_memcpy()
3748 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, in udma_prep_dma_memcpy()
3751 if (uc->config.metadata_size) in udma_prep_dma_memcpy()
3752 d->vd.tx.metadata_ops = &metadata_ops; in udma_prep_dma_memcpy()
3754 return vchan_tx_prep(&uc->vc, &d->vd, tx_flags); in udma_prep_dma_memcpy()
3762 spin_lock_irqsave(&uc->vc.lock, flags); in udma_issue_pending()
3765 if (vchan_issue_pending(&uc->vc) && !uc->desc) { in udma_issue_pending()
3771 if (!(uc->state == UDMA_CHAN_IS_TERMINATING && in udma_issue_pending()
3776 spin_unlock_irqrestore(&uc->vc.lock, flags); in udma_issue_pending()
3787 spin_lock_irqsave(&uc->vc.lock, flags); in udma_tx_status()
3800 if (uc->desc && uc->desc->vd.tx.cookie == cookie) { in udma_tx_status()
3803 u32 residue = uc->desc->residue; in udma_tx_status()
3806 if (uc->desc->dir == DMA_MEM_TO_DEV) { in udma_tx_status()
3809 if (uc->config.ep_type != PSIL_EP_NATIVE) { in udma_tx_status()
3814 delay = bcnt - peer_bcnt; in udma_tx_status()
3816 } else if (uc->desc->dir == DMA_DEV_TO_MEM) { in udma_tx_status()
3819 if (uc->config.ep_type != PSIL_EP_NATIVE) { in udma_tx_status()
3824 delay = peer_bcnt - bcnt; in udma_tx_status()
3830 if (bcnt && !(bcnt % uc->desc->residue)) in udma_tx_status()
3833 residue -= bcnt % uc->desc->residue; in udma_tx_status()
3835 if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) { in udma_tx_status()
3848 spin_unlock_irqrestore(&uc->vc.lock, flags); in udma_tx_status()
3857 switch (uc->config.dir) { in udma_pause()
3874 return -EINVAL; in udma_pause()
3885 switch (uc->config.dir) { in udma_resume()
3900 return -EINVAL; in udma_resume()
3912 spin_lock_irqsave(&uc->vc.lock, flags); in udma_terminate_all()
3917 if (uc->desc) { in udma_terminate_all()
3918 uc->terminated_desc = uc->desc; in udma_terminate_all()
3919 uc->desc = NULL; in udma_terminate_all()
3920 uc->terminated_desc->terminated = true; in udma_terminate_all()
3921 cancel_delayed_work(&uc->tx_drain.work); in udma_terminate_all()
3924 uc->paused = false; in udma_terminate_all()
3926 vchan_get_all_descriptors(&uc->vc, &head); in udma_terminate_all()
3927 spin_unlock_irqrestore(&uc->vc.lock, flags); in udma_terminate_all()
3928 vchan_dma_desc_free_list(&uc->vc, &head); in udma_terminate_all()
3938 vchan_synchronize(&uc->vc); in udma_synchronize()
3940 if (uc->state == UDMA_CHAN_IS_TERMINATING) { in udma_synchronize()
3941 timeout = wait_for_completion_timeout(&uc->teardown_completed, in udma_synchronize()
3944 dev_warn(uc->ud->dev, "chan%d teardown timeout!\n", in udma_synchronize()
3945 uc->id); in udma_synchronize()
3953 dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); in udma_synchronize()
3955 cancel_delayed_work_sync(&uc->tx_drain.work); in udma_synchronize()
3963 struct udma_chan *uc = to_udma_chan(&vc->chan); in udma_desc_pre_callback()
3969 d = to_udma_desc(&vd->tx); in udma_desc_pre_callback()
3971 if (d->metadata_size) in udma_desc_pre_callback()
3976 void *desc_vaddr = udma_curr_cppi5_desc_vaddr(d, d->desc_idx); in udma_desc_pre_callback()
3980 result->residue = d->residue - in udma_desc_pre_callback()
3982 if (result->residue) in udma_desc_pre_callback()
3983 result->result = DMA_TRANS_ABORTED; in udma_desc_pre_callback()
3985 result->result = DMA_TRANS_NOERROR; in udma_desc_pre_callback()
3987 result->residue = 0; in udma_desc_pre_callback()
3988 result->result = DMA_TRANS_NOERROR; in udma_desc_pre_callback()
4004 spin_lock_irq(&vc->lock); in udma_vchan_complete()
4005 list_splice_tail_init(&vc->desc_completed, &head); in udma_vchan_complete()
4006 vd = vc->cyclic; in udma_vchan_complete()
4008 vc->cyclic = NULL; in udma_vchan_complete()
4009 dmaengine_desc_get_callback(&vd->tx, &cb); in udma_vchan_complete()
4013 spin_unlock_irq(&vc->lock); in udma_vchan_complete()
4021 dmaengine_desc_get_callback(&vd->tx, &cb); in udma_vchan_complete()
4023 list_del(&vd->node); in udma_vchan_complete()
4035 struct udma_dev *ud = to_udma_dev(chan->device); in udma_free_chan_resources()
4038 if (uc->terminated_desc) { in udma_free_chan_resources()
4043 cancel_delayed_work_sync(&uc->tx_drain.work); in udma_free_chan_resources()
4045 if (uc->irq_num_ring > 0) { in udma_free_chan_resources()
4046 free_irq(uc->irq_num_ring, uc); in udma_free_chan_resources()
4048 uc->irq_num_ring = 0; in udma_free_chan_resources()
4050 if (uc->irq_num_udma > 0) { in udma_free_chan_resources()
4051 free_irq(uc->irq_num_udma, uc); in udma_free_chan_resources()
4053 uc->irq_num_udma = 0; in udma_free_chan_resources()
4056 /* Release PSI-L pairing */ in udma_free_chan_resources()
4057 if (uc->psil_paired) { in udma_free_chan_resources()
4058 navss_psil_unpair(ud, uc->config.src_thread, in udma_free_chan_resources()
4059 uc->config.dst_thread); in udma_free_chan_resources()
4060 uc->psil_paired = false; in udma_free_chan_resources()
4063 vchan_free_chan_resources(&uc->vc); in udma_free_chan_resources()
4064 tasklet_kill(&uc->vc.task); in udma_free_chan_resources()
4071 if (uc->use_dma_pool) { in udma_free_chan_resources()
4072 dma_pool_destroy(uc->hdesc_pool); in udma_free_chan_resources()
4073 uc->use_dma_pool = false; in udma_free_chan_resources()
4096 if (chan->device->dev->driver != &udma_driver.driver && in udma_dma_filter_fn()
4097 chan->device->dev->driver != &bcdma_driver.driver && in udma_dma_filter_fn()
4098 chan->device->dev->driver != &pktdma_driver.driver) in udma_dma_filter_fn()
4102 ucc = &uc->config; in udma_dma_filter_fn()
4103 ud = uc->ud; in udma_dma_filter_fn()
4106 if (filter_param->atype > 2) { in udma_dma_filter_fn()
4107 dev_err(ud->dev, "Invalid channel atype: %u\n", in udma_dma_filter_fn()
4108 filter_param->atype); in udma_dma_filter_fn()
4112 if (filter_param->asel > 15) { in udma_dma_filter_fn()
4113 dev_err(ud->dev, "Invalid channel asel: %u\n", in udma_dma_filter_fn()
4114 filter_param->asel); in udma_dma_filter_fn()
4118 ucc->remote_thread_id = filter_param->remote_thread_id; in udma_dma_filter_fn()
4119 ucc->atype = filter_param->atype; in udma_dma_filter_fn()
4120 ucc->asel = filter_param->asel; in udma_dma_filter_fn()
4121 ucc->tr_trigger_type = filter_param->tr_trigger_type; in udma_dma_filter_fn()
4123 if (ucc->tr_trigger_type) { in udma_dma_filter_fn()
4124 ucc->dir = DMA_MEM_TO_MEM; in udma_dma_filter_fn()
4126 } else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) { in udma_dma_filter_fn()
4127 ucc->dir = DMA_MEM_TO_DEV; in udma_dma_filter_fn()
4129 ucc->dir = DMA_DEV_TO_MEM; in udma_dma_filter_fn()
4132 ep_config = psil_get_ep_config(ucc->remote_thread_id); in udma_dma_filter_fn()
4134 dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n", in udma_dma_filter_fn()
4135 ucc->remote_thread_id); in udma_dma_filter_fn()
4136 ucc->dir = DMA_MEM_TO_MEM; in udma_dma_filter_fn()
4137 ucc->remote_thread_id = -1; in udma_dma_filter_fn()
4138 ucc->atype = 0; in udma_dma_filter_fn()
4139 ucc->asel = 0; in udma_dma_filter_fn()
4143 if (ud->match_data->type == DMA_TYPE_BCDMA && in udma_dma_filter_fn()
4144 ep_config->pkt_mode) { in udma_dma_filter_fn()
4145 dev_err(ud->dev, in udma_dma_filter_fn()
4146 "Only TR mode is supported (psi-l thread 0x%04x)\n", in udma_dma_filter_fn()
4147 ucc->remote_thread_id); in udma_dma_filter_fn()
4148 ucc->dir = DMA_MEM_TO_MEM; in udma_dma_filter_fn()
4149 ucc->remote_thread_id = -1; in udma_dma_filter_fn()
4150 ucc->atype = 0; in udma_dma_filter_fn()
4151 ucc->asel = 0; in udma_dma_filter_fn()
4155 ucc->pkt_mode = ep_config->pkt_mode; in udma_dma_filter_fn()
4156 ucc->channel_tpl = ep_config->channel_tpl; in udma_dma_filter_fn()
4157 ucc->notdpkt = ep_config->notdpkt; in udma_dma_filter_fn()
4158 ucc->ep_type = ep_config->ep_type; in udma_dma_filter_fn()
4160 if (ud->match_data->type == DMA_TYPE_PKTDMA && in udma_dma_filter_fn()
4161 ep_config->mapped_channel_id >= 0) { in udma_dma_filter_fn()
4162 ucc->mapped_channel_id = ep_config->mapped_channel_id; in udma_dma_filter_fn()
4163 ucc->default_flow_id = ep_config->default_flow_id; in udma_dma_filter_fn()
4165 ucc->mapped_channel_id = -1; in udma_dma_filter_fn()
4166 ucc->default_flow_id = -1; in udma_dma_filter_fn()
4169 if (ucc->ep_type != PSIL_EP_NATIVE) { in udma_dma_filter_fn()
4170 const struct udma_match_data *match_data = ud->match_data; in udma_dma_filter_fn()
4172 if (match_data->flags & UDMA_FLAG_PDMA_ACC32) in udma_dma_filter_fn()
4173 ucc->enable_acc32 = ep_config->pdma_acc32; in udma_dma_filter_fn()
4174 if (match_data->flags & UDMA_FLAG_PDMA_BURST) in udma_dma_filter_fn()
4175 ucc->enable_burst = ep_config->pdma_burst; in udma_dma_filter_fn()
4178 ucc->needs_epib = ep_config->needs_epib; in udma_dma_filter_fn()
4179 ucc->psd_size = ep_config->psd_size; in udma_dma_filter_fn()
4180 ucc->metadata_size = in udma_dma_filter_fn()
4181 (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + in udma_dma_filter_fn()
4182 ucc->psd_size; in udma_dma_filter_fn()
4184 if (ucc->pkt_mode) in udma_dma_filter_fn()
4185 ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + in udma_dma_filter_fn()
4186 ucc->metadata_size, ud->desc_align); in udma_dma_filter_fn()
4188 dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id, in udma_dma_filter_fn()
4189 ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir)); in udma_dma_filter_fn()
4194 dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id, in udma_dma_filter_fn()
4195 ucc->tr_trigger_type); in udma_dma_filter_fn()
4204 struct udma_dev *ud = ofdma->of_dma_data; in udma_of_xlate()
4205 dma_cap_mask_t mask = ud->ddev.cap_mask; in udma_of_xlate()
4209 if (ud->match_data->type == DMA_TYPE_BCDMA) { in udma_of_xlate()
4210 if (dma_spec->args_count != 3) in udma_of_xlate()
4213 filter_param.tr_trigger_type = dma_spec->args[0]; in udma_of_xlate()
4214 filter_param.remote_thread_id = dma_spec->args[1]; in udma_of_xlate()
4215 filter_param.asel = dma_spec->args[2]; in udma_of_xlate()
4218 if (dma_spec->args_count != 1 && dma_spec->args_count != 2) in udma_of_xlate()
4221 filter_param.remote_thread_id = dma_spec->args[0]; in udma_of_xlate()
4223 if (dma_spec->args_count == 2) { in udma_of_xlate()
4224 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_of_xlate()
4225 filter_param.atype = dma_spec->args[1]; in udma_of_xlate()
4229 filter_param.asel = dma_spec->args[1]; in udma_of_xlate()
4238 ofdma->of_node); in udma_of_xlate()
4240 dev_err(ud->dev, "get channel fail in %s.\n", __func__); in udma_of_xlate()
4241 return ERR_PTR(-EINVAL); in udma_of_xlate()
4299 .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
4325 .compatible = "ti,am654-navss-main-udmap",
4329 .compatible = "ti,am654-navss-mcu-udmap",
4332 .compatible = "ti,j721e-navss-main-udmap",
4335 .compatible = "ti,j721e-navss-mcu-udmap",
4343 .compatible = "ti,am64-dmss-bcdma",
4351 .compatible = "ti,am64-dmss-pktdma",
4404 ud->mmrs[MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev, mmr_names[MMR_GCFG]); in udma_get_mmrs()
4405 if (IS_ERR(ud->mmrs[MMR_GCFG])) in udma_get_mmrs()
4406 return PTR_ERR(ud->mmrs[MMR_GCFG]); in udma_get_mmrs()
4408 cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28); in udma_get_mmrs()
4409 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in udma_get_mmrs()
4411 switch (ud->match_data->type) { in udma_get_mmrs()
4413 ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3); in udma_get_mmrs()
4414 ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2); in udma_get_mmrs()
4415 ud->echan_cnt = UDMA_CAP2_ECHAN_CNT(cap2); in udma_get_mmrs()
4416 ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2); in udma_get_mmrs()
4419 ud->bchan_cnt = BCDMA_CAP2_BCHAN_CNT(cap2); in udma_get_mmrs()
4420 ud->tchan_cnt = BCDMA_CAP2_TCHAN_CNT(cap2); in udma_get_mmrs()
4421 ud->rchan_cnt = BCDMA_CAP2_RCHAN_CNT(cap2); in udma_get_mmrs()
4422 ud->rflow_cnt = ud->rchan_cnt; in udma_get_mmrs()
4425 cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30); in udma_get_mmrs()
4426 ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2); in udma_get_mmrs()
4427 ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2); in udma_get_mmrs()
4428 ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3); in udma_get_mmrs()
4429 ud->tflow_cnt = PKTDMA_CAP4_TFLOW_CNT(cap4); in udma_get_mmrs()
4432 return -EINVAL; in udma_get_mmrs()
4436 if (i == MMR_BCHANRT && ud->bchan_cnt == 0) in udma_get_mmrs()
4438 if (i == MMR_TCHANRT && ud->tchan_cnt == 0) in udma_get_mmrs()
4440 if (i == MMR_RCHANRT && ud->rchan_cnt == 0) in udma_get_mmrs()
4443 ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, mmr_names[i]); in udma_get_mmrs()
4444 if (IS_ERR(ud->mmrs[i])) in udma_get_mmrs()
4445 return PTR_ERR(ud->mmrs[i]); in udma_get_mmrs()
4455 bitmap_clear(map, rm_desc->start, rm_desc->num); in udma_mark_resource_ranges()
4456 bitmap_clear(map, rm_desc->start_sec, rm_desc->num_sec); in udma_mark_resource_ranges()
4457 dev_dbg(ud->dev, "ti_sci resource range for %s: %d:%d | %d:%d\n", name, in udma_mark_resource_ranges()
4458 rm_desc->start, rm_desc->num, rm_desc->start_sec, in udma_mark_resource_ranges()
4459 rm_desc->num_sec); in udma_mark_resource_ranges()
4463 [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
4464 [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
4465 [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
4466 [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
4467 [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
4473 struct device *dev = ud->dev; in udma_setup_resources()
4475 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in udma_setup_resources()
4479 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in udma_setup_resources()
4480 if (of_device_is_compatible(dev->of_node, in udma_setup_resources()
4481 "ti,am654-navss-main-udmap")) { in udma_setup_resources()
4482 ud->tchan_tpl.levels = 2; in udma_setup_resources()
4483 ud->tchan_tpl.start_idx[0] = 8; in udma_setup_resources()
4484 } else if (of_device_is_compatible(dev->of_node, in udma_setup_resources()
4485 "ti,am654-navss-mcu-udmap")) { in udma_setup_resources()
4486 ud->tchan_tpl.levels = 2; in udma_setup_resources()
4487 ud->tchan_tpl.start_idx[0] = 2; in udma_setup_resources()
4489 ud->tchan_tpl.levels = 3; in udma_setup_resources()
4490 ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); in udma_setup_resources()
4491 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in udma_setup_resources()
4493 ud->tchan_tpl.levels = 2; in udma_setup_resources()
4494 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in udma_setup_resources()
4496 ud->tchan_tpl.levels = 1; in udma_setup_resources()
4499 ud->rchan_tpl.levels = ud->tchan_tpl.levels; in udma_setup_resources()
4500 ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; in udma_setup_resources()
4501 ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; in udma_setup_resources()
4503 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), in udma_setup_resources()
4505 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), in udma_setup_resources()
4507 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), in udma_setup_resources()
4509 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), in udma_setup_resources()
4511 ud->rflow_gp_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rflow_cnt), in udma_setup_resources()
4514 ud->rflow_gp_map_allocated = devm_kcalloc(dev, in udma_setup_resources()
4515 BITS_TO_LONGS(ud->rflow_cnt), in udma_setup_resources()
4518 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), in udma_setup_resources()
4521 ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), in udma_setup_resources()
4524 if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_gp_map || in udma_setup_resources()
4525 !ud->rflow_gp_map_allocated || !ud->tchans || !ud->rchans || in udma_setup_resources()
4526 !ud->rflows || !ud->rflow_in_use) in udma_setup_resources()
4527 return -ENOMEM; in udma_setup_resources()
4534 bitmap_set(ud->rflow_gp_map_allocated, 0, ud->rchan_cnt); in udma_setup_resources()
4537 bitmap_set(ud->rflow_gp_map, 0, ud->rflow_cnt); in udma_setup_resources()
4544 tisci_rm->rm_ranges[i] = in udma_setup_resources()
4545 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, in udma_setup_resources()
4546 tisci_rm->tisci_dev_id, in udma_setup_resources()
4551 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in udma_setup_resources()
4553 bitmap_zero(ud->tchan_map, ud->tchan_cnt); in udma_setup_resources()
4556 bitmap_fill(ud->tchan_map, ud->tchan_cnt); in udma_setup_resources()
4557 for (i = 0; i < rm_res->sets; i++) in udma_setup_resources()
4558 udma_mark_resource_ranges(ud, ud->tchan_map, in udma_setup_resources()
4559 &rm_res->desc[i], "tchan"); in udma_setup_resources()
4560 irq_res.sets = rm_res->sets; in udma_setup_resources()
4563 /* rchan and matching default flow ranges */ in udma_setup_resources()
4564 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in udma_setup_resources()
4566 bitmap_zero(ud->rchan_map, ud->rchan_cnt); in udma_setup_resources()
4569 bitmap_fill(ud->rchan_map, ud->rchan_cnt); in udma_setup_resources()
4570 for (i = 0; i < rm_res->sets; i++) in udma_setup_resources()
4571 udma_mark_resource_ranges(ud, ud->rchan_map, in udma_setup_resources()
4572 &rm_res->desc[i], "rchan"); in udma_setup_resources()
4573 irq_res.sets += rm_res->sets; in udma_setup_resources()
4578 return -ENOMEM; in udma_setup_resources()
4579 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in udma_setup_resources()
4582 irq_res.desc[0].num = ud->tchan_cnt; in udma_setup_resources()
4585 for (i = 0; i < rm_res->sets; i++) { in udma_setup_resources()
4586 irq_res.desc[i].start = rm_res->desc[i].start; in udma_setup_resources()
4587 irq_res.desc[i].num = rm_res->desc[i].num; in udma_setup_resources()
4588 irq_res.desc[i].start_sec = rm_res->desc[i].start_sec; in udma_setup_resources()
4589 irq_res.desc[i].num_sec = rm_res->desc[i].num_sec; in udma_setup_resources()
4592 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in udma_setup_resources()
4595 irq_res.desc[i].num = ud->rchan_cnt; in udma_setup_resources()
4597 for (j = 0; j < rm_res->sets; j++, i++) { in udma_setup_resources()
4598 if (rm_res->desc[j].num) { in udma_setup_resources()
4599 irq_res.desc[i].start = rm_res->desc[j].start + in udma_setup_resources()
4600 ud->soc_data->oes.udma_rchan; in udma_setup_resources()
4601 irq_res.desc[i].num = rm_res->desc[j].num; in udma_setup_resources()
4603 if (rm_res->desc[j].num_sec) { in udma_setup_resources()
4604 irq_res.desc[i].start_sec = rm_res->desc[j].start_sec + in udma_setup_resources()
4605 ud->soc_data->oes.udma_rchan; in udma_setup_resources()
4606 irq_res.desc[i].num_sec = rm_res->desc[j].num_sec; in udma_setup_resources()
4610 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); in udma_setup_resources()
4613 dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); in udma_setup_resources()
4618 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; in udma_setup_resources()
4621 bitmap_clear(ud->rflow_gp_map, ud->rchan_cnt, in udma_setup_resources()
4622 ud->rflow_cnt - ud->rchan_cnt); in udma_setup_resources()
4624 for (i = 0; i < rm_res->sets; i++) in udma_setup_resources()
4625 udma_mark_resource_ranges(ud, ud->rflow_gp_map, in udma_setup_resources()
4626 &rm_res->desc[i], "gp-rflow"); in udma_setup_resources()
4635 struct device *dev = ud->dev; in bcdma_setup_resources()
4637 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in bcdma_setup_resources()
4638 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in bcdma_setup_resources()
4642 cap = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in bcdma_setup_resources()
4644 ud->bchan_tpl.levels = 3; in bcdma_setup_resources()
4645 ud->bchan_tpl.start_idx[1] = BCDMA_CAP3_UBCHAN_CNT(cap); in bcdma_setup_resources()
4646 ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); in bcdma_setup_resources()
4648 ud->bchan_tpl.levels = 2; in bcdma_setup_resources()
4649 ud->bchan_tpl.start_idx[0] = BCDMA_CAP3_HBCHAN_CNT(cap); in bcdma_setup_resources()
4651 ud->bchan_tpl.levels = 1; in bcdma_setup_resources()
4654 cap = udma_read(ud->mmrs[MMR_GCFG], 0x30); in bcdma_setup_resources()
4656 ud->rchan_tpl.levels = 3; in bcdma_setup_resources()
4657 ud->rchan_tpl.start_idx[1] = BCDMA_CAP4_URCHAN_CNT(cap); in bcdma_setup_resources()
4658 ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); in bcdma_setup_resources()
4660 ud->rchan_tpl.levels = 2; in bcdma_setup_resources()
4661 ud->rchan_tpl.start_idx[0] = BCDMA_CAP4_HRCHAN_CNT(cap); in bcdma_setup_resources()
4663 ud->rchan_tpl.levels = 1; in bcdma_setup_resources()
4667 ud->tchan_tpl.levels = 3; in bcdma_setup_resources()
4668 ud->tchan_tpl.start_idx[1] = BCDMA_CAP4_UTCHAN_CNT(cap); in bcdma_setup_resources()
4669 ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); in bcdma_setup_resources()
4671 ud->tchan_tpl.levels = 2; in bcdma_setup_resources()
4672 ud->tchan_tpl.start_idx[0] = BCDMA_CAP4_HTCHAN_CNT(cap); in bcdma_setup_resources()
4674 ud->tchan_tpl.levels = 1; in bcdma_setup_resources()
4677 ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt), in bcdma_setup_resources()
4679 ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans), in bcdma_setup_resources()
4681 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), in bcdma_setup_resources()
4683 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), in bcdma_setup_resources()
4685 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), in bcdma_setup_resources()
4687 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), in bcdma_setup_resources()
4690 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt), in bcdma_setup_resources()
4693 ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), in bcdma_setup_resources()
4696 if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || in bcdma_setup_resources()
4697 !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans || in bcdma_setup_resources()
4698 !ud->rflows) in bcdma_setup_resources()
4699 return -ENOMEM; in bcdma_setup_resources()
4705 if (i == RM_RANGE_BCHAN && ud->bchan_cnt == 0) in bcdma_setup_resources()
4707 if (i == RM_RANGE_TCHAN && ud->tchan_cnt == 0) in bcdma_setup_resources()
4709 if (i == RM_RANGE_RCHAN && ud->rchan_cnt == 0) in bcdma_setup_resources()
4712 tisci_rm->rm_ranges[i] = in bcdma_setup_resources()
4713 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, in bcdma_setup_resources()
4714 tisci_rm->tisci_dev_id, in bcdma_setup_resources()
4721 if (ud->bchan_cnt) { in bcdma_setup_resources()
4722 rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; in bcdma_setup_resources()
4724 bitmap_zero(ud->bchan_map, ud->bchan_cnt); in bcdma_setup_resources()
4727 bitmap_fill(ud->bchan_map, ud->bchan_cnt); in bcdma_setup_resources()
4728 for (i = 0; i < rm_res->sets; i++) in bcdma_setup_resources()
4729 udma_mark_resource_ranges(ud, ud->bchan_map, in bcdma_setup_resources()
4730 &rm_res->desc[i], in bcdma_setup_resources()
4732 irq_res.sets += rm_res->sets; in bcdma_setup_resources()
4737 if (ud->tchan_cnt) { in bcdma_setup_resources()
4738 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in bcdma_setup_resources()
4740 bitmap_zero(ud->tchan_map, ud->tchan_cnt); in bcdma_setup_resources()
4743 bitmap_fill(ud->tchan_map, ud->tchan_cnt); in bcdma_setup_resources()
4744 for (i = 0; i < rm_res->sets; i++) in bcdma_setup_resources()
4745 udma_mark_resource_ranges(ud, ud->tchan_map, in bcdma_setup_resources()
4746 &rm_res->desc[i], in bcdma_setup_resources()
4748 irq_res.sets += rm_res->sets * 2; in bcdma_setup_resources()
4752 /* rchan ranges */ in bcdma_setup_resources()
4753 if (ud->rchan_cnt) { in bcdma_setup_resources()
4754 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in bcdma_setup_resources()
4756 bitmap_zero(ud->rchan_map, ud->rchan_cnt); in bcdma_setup_resources()
4759 bitmap_fill(ud->rchan_map, ud->rchan_cnt); in bcdma_setup_resources()
4760 for (i = 0; i < rm_res->sets; i++) in bcdma_setup_resources()
4761 udma_mark_resource_ranges(ud, ud->rchan_map, in bcdma_setup_resources()
4762 &rm_res->desc[i], in bcdma_setup_resources()
4763 "rchan"); in bcdma_setup_resources()
4764 irq_res.sets += rm_res->sets * 2; in bcdma_setup_resources()
4770 return -ENOMEM; in bcdma_setup_resources()
4771 if (ud->bchan_cnt) { in bcdma_setup_resources()
4772 rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN]; in bcdma_setup_resources()
4774 irq_res.desc[0].start = oes->bcdma_bchan_ring; in bcdma_setup_resources()
4775 irq_res.desc[0].num = ud->bchan_cnt; in bcdma_setup_resources()
4778 for (i = 0; i < rm_res->sets; i++) { in bcdma_setup_resources()
4779 irq_res.desc[i].start = rm_res->desc[i].start + in bcdma_setup_resources()
4780 oes->bcdma_bchan_ring; in bcdma_setup_resources()
4781 irq_res.desc[i].num = rm_res->desc[i].num; in bcdma_setup_resources()
4785 if (ud->tchan_cnt) { in bcdma_setup_resources()
4786 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in bcdma_setup_resources()
4788 irq_res.desc[i].start = oes->bcdma_tchan_data; in bcdma_setup_resources()
4789 irq_res.desc[i].num = ud->tchan_cnt; in bcdma_setup_resources()
4790 irq_res.desc[i + 1].start = oes->bcdma_tchan_ring; in bcdma_setup_resources()
4791 irq_res.desc[i + 1].num = ud->tchan_cnt; in bcdma_setup_resources()
4794 for (j = 0; j < rm_res->sets; j++, i += 2) { in bcdma_setup_resources()
4795 irq_res.desc[i].start = rm_res->desc[j].start + in bcdma_setup_resources()
4796 oes->bcdma_tchan_data; in bcdma_setup_resources()
4797 irq_res.desc[i].num = rm_res->desc[j].num; in bcdma_setup_resources()
4799 irq_res.desc[i + 1].start = rm_res->desc[j].start + in bcdma_setup_resources()
4800 oes->bcdma_tchan_ring; in bcdma_setup_resources()
4801 irq_res.desc[i + 1].num = rm_res->desc[j].num; in bcdma_setup_resources()
4805 if (ud->rchan_cnt) { in bcdma_setup_resources()
4806 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in bcdma_setup_resources()
4808 irq_res.desc[i].start = oes->bcdma_rchan_data; in bcdma_setup_resources()
4809 irq_res.desc[i].num = ud->rchan_cnt; in bcdma_setup_resources()
4810 irq_res.desc[i + 1].start = oes->bcdma_rchan_ring; in bcdma_setup_resources()
4811 irq_res.desc[i + 1].num = ud->rchan_cnt; in bcdma_setup_resources()
4814 for (j = 0; j < rm_res->sets; j++, i += 2) { in bcdma_setup_resources()
4815 irq_res.desc[i].start = rm_res->desc[j].start + in bcdma_setup_resources()
4816 oes->bcdma_rchan_data; in bcdma_setup_resources()
4817 irq_res.desc[i].num = rm_res->desc[j].num; in bcdma_setup_resources()
4819 irq_res.desc[i + 1].start = rm_res->desc[j].start + in bcdma_setup_resources()
4820 oes->bcdma_rchan_ring; in bcdma_setup_resources()
4821 irq_res.desc[i + 1].num = rm_res->desc[j].num; in bcdma_setup_resources()
4826 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); in bcdma_setup_resources()
4829 dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); in bcdma_setup_resources()
4839 struct device *dev = ud->dev; in pktdma_setup_resources()
4841 struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; in pktdma_setup_resources()
4842 const struct udma_oes_offsets *oes = &ud->soc_data->oes; in pktdma_setup_resources()
4846 cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c); in pktdma_setup_resources()
4848 ud->tchan_tpl.levels = 3; in pktdma_setup_resources()
4849 ud->tchan_tpl.start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3); in pktdma_setup_resources()
4850 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in pktdma_setup_resources()
4852 ud->tchan_tpl.levels = 2; in pktdma_setup_resources()
4853 ud->tchan_tpl.start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3); in pktdma_setup_resources()
4855 ud->tchan_tpl.levels = 1; in pktdma_setup_resources()
4858 ud->rchan_tpl.levels = ud->tchan_tpl.levels; in pktdma_setup_resources()
4859 ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0]; in pktdma_setup_resources()
4860 ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1]; in pktdma_setup_resources()
4862 ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), in pktdma_setup_resources()
4864 ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), in pktdma_setup_resources()
4866 ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), in pktdma_setup_resources()
4868 ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), in pktdma_setup_resources()
4870 ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), in pktdma_setup_resources()
4873 ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), in pktdma_setup_resources()
4875 ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), in pktdma_setup_resources()
4878 if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || in pktdma_setup_resources()
4879 !ud->rchans || !ud->rflows || !ud->rflow_in_use) in pktdma_setup_resources()
4880 return -ENOMEM; in pktdma_setup_resources()
4887 tisci_rm->rm_ranges[i] = in pktdma_setup_resources()
4888 devm_ti_sci_get_of_resource(tisci_rm->tisci, dev, in pktdma_setup_resources()
4889 tisci_rm->tisci_dev_id, in pktdma_setup_resources()
4894 rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN]; in pktdma_setup_resources()
4896 bitmap_zero(ud->tchan_map, ud->tchan_cnt); in pktdma_setup_resources()
4898 bitmap_fill(ud->tchan_map, ud->tchan_cnt); in pktdma_setup_resources()
4899 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
4900 udma_mark_resource_ranges(ud, ud->tchan_map, in pktdma_setup_resources()
4901 &rm_res->desc[i], "tchan"); in pktdma_setup_resources()
4904 /* rchan ranges */ in pktdma_setup_resources()
4905 rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN]; in pktdma_setup_resources()
4907 bitmap_zero(ud->rchan_map, ud->rchan_cnt); in pktdma_setup_resources()
4909 bitmap_fill(ud->rchan_map, ud->rchan_cnt); in pktdma_setup_resources()
4910 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
4911 udma_mark_resource_ranges(ud, ud->rchan_map, in pktdma_setup_resources()
4912 &rm_res->desc[i], "rchan"); in pktdma_setup_resources()
4916 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; in pktdma_setup_resources()
4919 bitmap_zero(ud->rflow_in_use, ud->rflow_cnt); in pktdma_setup_resources()
4922 bitmap_fill(ud->rflow_in_use, ud->rflow_cnt); in pktdma_setup_resources()
4923 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
4924 udma_mark_resource_ranges(ud, ud->rflow_in_use, in pktdma_setup_resources()
4925 &rm_res->desc[i], "rflow"); in pktdma_setup_resources()
4926 irq_res.sets = rm_res->sets; in pktdma_setup_resources()
4930 rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; in pktdma_setup_resources()
4933 bitmap_zero(ud->tflow_map, ud->tflow_cnt); in pktdma_setup_resources()
4936 bitmap_fill(ud->tflow_map, ud->tflow_cnt); in pktdma_setup_resources()
4937 for (i = 0; i < rm_res->sets; i++) in pktdma_setup_resources()
4938 udma_mark_resource_ranges(ud, ud->tflow_map, in pktdma_setup_resources()
4939 &rm_res->desc[i], "tflow"); in pktdma_setup_resources()
4940 irq_res.sets += rm_res->sets; in pktdma_setup_resources()
4945 return -ENOMEM; in pktdma_setup_resources()
4946 rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW]; in pktdma_setup_resources()
4948 irq_res.desc[0].start = oes->pktdma_tchan_flow; in pktdma_setup_resources()
4949 irq_res.desc[0].num = ud->tflow_cnt; in pktdma_setup_resources()
4952 for (i = 0; i < rm_res->sets; i++) { in pktdma_setup_resources()
4953 irq_res.desc[i].start = rm_res->desc[i].start + in pktdma_setup_resources()
4954 oes->pktdma_tchan_flow; in pktdma_setup_resources()
4955 irq_res.desc[i].num = rm_res->desc[i].num; in pktdma_setup_resources()
4958 rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW]; in pktdma_setup_resources()
4960 irq_res.desc[i].start = oes->pktdma_rchan_flow; in pktdma_setup_resources()
4961 irq_res.desc[i].num = ud->rflow_cnt; in pktdma_setup_resources()
4963 for (j = 0; j < rm_res->sets; j++, i++) { in pktdma_setup_resources()
4964 irq_res.desc[i].start = rm_res->desc[j].start + in pktdma_setup_resources()
4965 oes->pktdma_rchan_flow; in pktdma_setup_resources()
4966 irq_res.desc[i].num = rm_res->desc[j].num; in pktdma_setup_resources()
4969 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res); in pktdma_setup_resources()
4972 dev_err(ud->dev, "Failed to allocate MSI interrupts\n"); in pktdma_setup_resources()
4981 struct device *dev = ud->dev; in setup_resources()
4984 switch (ud->match_data->type) { in setup_resources()
4995 return -EINVAL; in setup_resources()
5001 ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt; in setup_resources()
5002 if (ud->bchan_cnt) in setup_resources()
5003 ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt); in setup_resources()
5004 ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt); in setup_resources()
5005 ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt); in setup_resources()
5007 return -ENODEV; in setup_resources()
5009 ud->channels = devm_kcalloc(dev, ch_count, sizeof(*ud->channels), in setup_resources()
5011 if (!ud->channels) in setup_resources()
5012 return -ENOMEM; in setup_resources()
5014 switch (ud->match_data->type) { in setup_resources()
5017 "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n", in setup_resources()
5019 ud->tchan_cnt - bitmap_weight(ud->tchan_map, in setup_resources()
5020 ud->tchan_cnt), in setup_resources()
5021 ud->rchan_cnt - bitmap_weight(ud->rchan_map, in setup_resources()
5022 ud->rchan_cnt), in setup_resources()
5023 ud->rflow_cnt - bitmap_weight(ud->rflow_gp_map, in setup_resources()
5024 ud->rflow_cnt)); in setup_resources()
5028 "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n", in setup_resources()
5030 ud->bchan_cnt - bitmap_weight(ud->bchan_map, in setup_resources()
5031 ud->bchan_cnt), in setup_resources()
5032 ud->tchan_cnt - bitmap_weight(ud->tchan_map, in setup_resources()
5033 ud->tchan_cnt), in setup_resources()
5034 ud->rchan_cnt - bitmap_weight(ud->rchan_map, in setup_resources()
5035 ud->rchan_cnt)); in setup_resources()
5039 "Channels: %d (tchan: %u, rchan: %u)\n", in setup_resources()
5041 ud->tchan_cnt - bitmap_weight(ud->tchan_map, in setup_resources()
5042 ud->tchan_cnt), in setup_resources()
5043 ud->rchan_cnt - bitmap_weight(ud->rchan_map, in setup_resources()
5044 ud->rchan_cnt)); in setup_resources()
5055 struct udma_rx_flush *rx_flush = &ud->rx_flush; in udma_setup_rx_flush()
5059 struct device *dev = ud->dev; in udma_setup_rx_flush()
5064 rx_flush->buffer_size = SZ_1K; in udma_setup_rx_flush()
5065 rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size, in udma_setup_rx_flush()
5067 if (!rx_flush->buffer_vaddr) in udma_setup_rx_flush()
5068 return -ENOMEM; in udma_setup_rx_flush()
5070 rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr, in udma_setup_rx_flush()
5071 rx_flush->buffer_size, in udma_setup_rx_flush()
5073 if (dma_mapping_error(dev, rx_flush->buffer_paddr)) in udma_setup_rx_flush()
5074 return -ENOMEM; in udma_setup_rx_flush()
5077 hwdesc = &rx_flush->hwdescs[0]; in udma_setup_rx_flush()
5079 hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1); in udma_setup_rx_flush()
5080 hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5081 ud->desc_align); in udma_setup_rx_flush()
5083 hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5085 if (!hwdesc->cppi5_desc_vaddr) in udma_setup_rx_flush()
5086 return -ENOMEM; in udma_setup_rx_flush()
5088 hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, in udma_setup_rx_flush()
5089 hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5091 if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) in udma_setup_rx_flush()
5092 return -ENOMEM; in udma_setup_rx_flush()
5095 hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size; in udma_setup_rx_flush()
5097 hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size; in udma_setup_rx_flush()
5099 tr_desc = hwdesc->cppi5_desc_vaddr; in udma_setup_rx_flush()
5104 tr_req = hwdesc->tr_req_base; in udma_setup_rx_flush()
5105 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false, in udma_setup_rx_flush()
5107 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT); in udma_setup_rx_flush()
5109 tr_req->addr = rx_flush->buffer_paddr; in udma_setup_rx_flush()
5110 tr_req->icnt0 = rx_flush->buffer_size; in udma_setup_rx_flush()
5111 tr_req->icnt1 = 1; in udma_setup_rx_flush()
5113 dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, in udma_setup_rx_flush()
5114 hwdesc->cppi5_desc_size, DMA_TO_DEVICE); in udma_setup_rx_flush()
5117 hwdesc = &rx_flush->hwdescs[1]; in udma_setup_rx_flush()
5118 hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) + in udma_setup_rx_flush()
5121 ud->desc_align); in udma_setup_rx_flush()
5123 hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5125 if (!hwdesc->cppi5_desc_vaddr) in udma_setup_rx_flush()
5126 return -ENOMEM; in udma_setup_rx_flush()
5128 hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr, in udma_setup_rx_flush()
5129 hwdesc->cppi5_desc_size, in udma_setup_rx_flush()
5131 if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr)) in udma_setup_rx_flush()
5132 return -ENOMEM; in udma_setup_rx_flush()
5134 desc = hwdesc->cppi5_desc_vaddr; in udma_setup_rx_flush()
5136 cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT); in udma_setup_rx_flush()
5137 cppi5_desc_set_retpolicy(&desc->hdr, 0, 0); in udma_setup_rx_flush()
5140 rx_flush->buffer_paddr, rx_flush->buffer_size, in udma_setup_rx_flush()
5141 rx_flush->buffer_paddr, rx_flush->buffer_size); in udma_setup_rx_flush()
5143 dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr, in udma_setup_rx_flush()
5144 hwdesc->cppi5_desc_size, DMA_TO_DEVICE); in udma_setup_rx_flush()
5153 struct udma_chan_config *ucc = &uc->config; in udma_dbg_summary_show_chan()
5155 seq_printf(s, " %-13s| %s", dma_chan_name(chan), in udma_dbg_summary_show_chan()
5156 chan->dbg_client_name ?: "in-use"); in udma_dbg_summary_show_chan()
5157 if (ucc->tr_trigger_type) in udma_dbg_summary_show_chan()
5161 dmaengine_get_direction_text(uc->config.dir)); in udma_dbg_summary_show_chan()
5163 switch (uc->config.dir) { in udma_dbg_summary_show_chan()
5165 if (uc->ud->match_data->type == DMA_TYPE_BCDMA) { in udma_dbg_summary_show_chan()
5166 seq_printf(s, "bchan%d)\n", uc->bchan->id); in udma_dbg_summary_show_chan()
5170 seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id, in udma_dbg_summary_show_chan()
5171 ucc->src_thread, ucc->dst_thread); in udma_dbg_summary_show_chan()
5174 seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id, in udma_dbg_summary_show_chan()
5175 ucc->src_thread, ucc->dst_thread); in udma_dbg_summary_show_chan()
5176 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) in udma_dbg_summary_show_chan()
5177 seq_printf(s, "rflow%d, ", uc->rflow->id); in udma_dbg_summary_show_chan()
5180 seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id, in udma_dbg_summary_show_chan()
5181 ucc->src_thread, ucc->dst_thread); in udma_dbg_summary_show_chan()
5182 if (uc->ud->match_data->type == DMA_TYPE_PKTDMA) in udma_dbg_summary_show_chan()
5183 seq_printf(s, "tflow%d, ", uc->tchan->tflow_id); in udma_dbg_summary_show_chan()
5190 if (ucc->ep_type == PSIL_EP_NATIVE) { in udma_dbg_summary_show_chan()
5191 seq_printf(s, "PSI-L Native"); in udma_dbg_summary_show_chan()
5192 if (ucc->metadata_size) { in udma_dbg_summary_show_chan()
5193 seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : ""); in udma_dbg_summary_show_chan()
5194 if (ucc->psd_size) in udma_dbg_summary_show_chan()
5195 seq_printf(s, " PSDsize:%u", ucc->psd_size); in udma_dbg_summary_show_chan()
5200 if (ucc->enable_acc32 || ucc->enable_burst) in udma_dbg_summary_show_chan()
5202 ucc->enable_acc32 ? " ACC32" : "", in udma_dbg_summary_show_chan()
5203 ucc->enable_burst ? " BURST" : ""); in udma_dbg_summary_show_chan()
5206 seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode"); in udma_dbg_summary_show_chan()
5214 list_for_each_entry(chan, &dma_dev->channels, device_node) { in udma_dbg_summary_show()
5215 if (chan->client_count) in udma_dbg_summary_show()
5223 const struct udma_match_data *match_data = ud->match_data; in udma_get_copy_align()
5226 if (!match_data->enable_memcpy_support) in udma_get_copy_align()
5230 if (ud->bchan_cnt) in udma_get_copy_align()
5231 tpl = udma_get_chan_tpl_index(&ud->bchan_tpl, 0); in udma_get_copy_align()
5232 else if (ud->tchan_cnt) in udma_get_copy_align()
5233 tpl = udma_get_chan_tpl_index(&ud->tchan_tpl, 0); in udma_get_copy_align()
5237 switch (match_data->burst_size[tpl]) { in udma_get_copy_align()
5257 struct device_node *navss_node = pdev->dev.parent->of_node; in udma_probe()
5259 struct device *dev = &pdev->dev; in udma_probe()
5271 return -ENOMEM; in udma_probe()
5273 match = of_match_node(udma_of_match, dev->of_node); in udma_probe()
5275 match = of_match_node(bcdma_of_match, dev->of_node); in udma_probe()
5277 match = of_match_node(pktdma_of_match, dev->of_node); in udma_probe()
5280 return -ENODEV; in udma_probe()
5283 ud->match_data = match->data; in udma_probe()
5288 return -ENODEV; in udma_probe()
5290 ud->soc_data = soc->data; in udma_probe()
5296 ud->tisci_rm.tisci = ti_sci_get_by_phandle(dev->of_node, "ti,sci"); in udma_probe()
5297 if (IS_ERR(ud->tisci_rm.tisci)) in udma_probe()
5298 return PTR_ERR(ud->tisci_rm.tisci); in udma_probe()
5300 ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", in udma_probe()
5301 &ud->tisci_rm.tisci_dev_id); in udma_probe()
5303 dev_err(dev, "ti,sci-dev-id read failure %d\n", ret); in udma_probe()
5306 pdev->id = ud->tisci_rm.tisci_dev_id; in udma_probe()
5308 ret = of_property_read_u32(navss_node, "ti,sci-dev-id", in udma_probe()
5309 &ud->tisci_rm.tisci_navss_dev_id); in udma_probe()
5311 dev_err(dev, "NAVSS ti,sci-dev-id read failure %d\n", ret); in udma_probe()
5315 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_probe()
5316 ret = of_property_read_u32(dev->of_node, "ti,udma-atype", in udma_probe()
5317 &ud->atype); in udma_probe()
5318 if (!ret && ud->atype > 2) { in udma_probe()
5319 dev_err(dev, "Invalid atype: %u\n", ud->atype); in udma_probe()
5320 return -EINVAL; in udma_probe()
5323 ret = of_property_read_u32(dev->of_node, "ti,asel", in udma_probe()
5324 &ud->asel); in udma_probe()
5325 if (!ret && ud->asel > 15) { in udma_probe()
5326 dev_err(dev, "Invalid asel: %u\n", ud->asel); in udma_probe()
5327 return -EINVAL; in udma_probe()
5331 ud->tisci_rm.tisci_udmap_ops = &ud->tisci_rm.tisci->ops.rm_udmap_ops; in udma_probe()
5332 ud->tisci_rm.tisci_psil_ops = &ud->tisci_rm.tisci->ops.rm_psil_ops; in udma_probe()
5334 if (ud->match_data->type == DMA_TYPE_UDMA) { in udma_probe()
5335 ud->ringacc = of_k3_ringacc_get_by_phandle(dev->of_node, "ti,ringacc"); in udma_probe()
5339 ring_init_data.tisci = ud->tisci_rm.tisci; in udma_probe()
5340 ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id; in udma_probe()
5341 if (ud->match_data->type == DMA_TYPE_BCDMA) { in udma_probe()
5342 ring_init_data.num_rings = ud->bchan_cnt + in udma_probe()
5343 ud->tchan_cnt + in udma_probe()
5344 ud->rchan_cnt; in udma_probe()
5346 ring_init_data.num_rings = ud->rflow_cnt + in udma_probe()
5347 ud->tflow_cnt; in udma_probe()
5350 ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data); in udma_probe()
5353 if (IS_ERR(ud->ringacc)) in udma_probe()
5354 return PTR_ERR(ud->ringacc); in udma_probe()
5356 dev->msi.domain = of_msi_get_domain(dev, dev->of_node, in udma_probe()
5358 if (!dev->msi.domain) { in udma_probe()
5360 return -EPROBE_DEFER; in udma_probe()
5363 dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask); in udma_probe()
5365 if (ud->match_data->type != DMA_TYPE_PKTDMA) { in udma_probe()
5366 dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); in udma_probe()
5367 ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic; in udma_probe()
5370 ud->ddev.device_config = udma_slave_config; in udma_probe()
5371 ud->ddev.device_prep_slave_sg = udma_prep_slave_sg; in udma_probe()
5372 ud->ddev.device_issue_pending = udma_issue_pending; in udma_probe()
5373 ud->ddev.device_tx_status = udma_tx_status; in udma_probe()
5374 ud->ddev.device_pause = udma_pause; in udma_probe()
5375 ud->ddev.device_resume = udma_resume; in udma_probe()
5376 ud->ddev.device_terminate_all = udma_terminate_all; in udma_probe()
5377 ud->ddev.device_synchronize = udma_synchronize; in udma_probe()
5379 ud->ddev.dbg_summary_show = udma_dbg_summary_show; in udma_probe()
5382 switch (ud->match_data->type) { in udma_probe()
5384 ud->ddev.device_alloc_chan_resources = in udma_probe()
5388 ud->ddev.device_alloc_chan_resources = in udma_probe()
5390 ud->ddev.device_router_config = bcdma_router_config; in udma_probe()
5393 ud->ddev.device_alloc_chan_resources = in udma_probe()
5397 return -EINVAL; in udma_probe()
5399 ud->ddev.device_free_chan_resources = udma_free_chan_resources; in udma_probe()
5401 ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS; in udma_probe()
5402 ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS; in udma_probe()
5403 ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in udma_probe()
5404 ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in udma_probe()
5405 ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT | in udma_probe()
5407 if (ud->match_data->enable_memcpy_support && in udma_probe()
5408 !(ud->match_data->type == DMA_TYPE_BCDMA && ud->bchan_cnt == 0)) { in udma_probe()
5409 dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask); in udma_probe()
5410 ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy; in udma_probe()
5411 ud->ddev.directions |= BIT(DMA_MEM_TO_MEM); in udma_probe()
5414 ud->ddev.dev = dev; in udma_probe()
5415 ud->dev = dev; in udma_probe()
5416 ud->psil_base = ud->match_data->psil_base; in udma_probe()
5418 INIT_LIST_HEAD(&ud->ddev.channels); in udma_probe()
5419 INIT_LIST_HEAD(&ud->desc_to_purge); in udma_probe()
5425 spin_lock_init(&ud->lock); in udma_probe()
5426 INIT_WORK(&ud->purge_work, udma_purge_desc_work); in udma_probe()
5428 ud->desc_align = 64; in udma_probe()
5429 if (ud->desc_align < dma_get_cache_alignment()) in udma_probe()
5430 ud->desc_align = dma_get_cache_alignment(); in udma_probe()
5436 for (i = 0; i < ud->bchan_cnt; i++) { in udma_probe()
5437 struct udma_bchan *bchan = &ud->bchans[i]; in udma_probe()
5439 bchan->id = i; in udma_probe()
5440 bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000; in udma_probe()
5443 for (i = 0; i < ud->tchan_cnt; i++) { in udma_probe()
5444 struct udma_tchan *tchan = &ud->tchans[i]; in udma_probe()
5446 tchan->id = i; in udma_probe()
5447 tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + i * 0x1000; in udma_probe()
5450 for (i = 0; i < ud->rchan_cnt; i++) { in udma_probe()
5451 struct udma_rchan *rchan = &ud->rchans[i]; in udma_probe() local
5453 rchan->id = i; in udma_probe()
5454 rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + i * 0x1000; in udma_probe()
5457 for (i = 0; i < ud->rflow_cnt; i++) { in udma_probe()
5458 struct udma_rflow *rflow = &ud->rflows[i]; in udma_probe()
5460 rflow->id = i; in udma_probe()
5464 struct udma_chan *uc = &ud->channels[i]; in udma_probe()
5466 uc->ud = ud; in udma_probe()
5467 uc->vc.desc_free = udma_desc_free; in udma_probe()
5468 uc->id = i; in udma_probe()
5469 uc->bchan = NULL; in udma_probe()
5470 uc->tchan = NULL; in udma_probe()
5471 uc->rchan = NULL; in udma_probe()
5472 uc->config.remote_thread_id = -1; in udma_probe()
5473 uc->config.mapped_channel_id = -1; in udma_probe()
5474 uc->config.default_flow_id = -1; in udma_probe()
5475 uc->config.dir = DMA_MEM_TO_MEM; in udma_probe()
5476 uc->name = devm_kasprintf(dev, GFP_KERNEL, "%s chan%d", in udma_probe()
5479 vchan_init(&uc->vc, &ud->ddev); in udma_probe()
5481 tasklet_setup(&uc->vc.task, udma_vchan_complete); in udma_probe()
5482 init_completion(&uc->teardown_completed); in udma_probe()
5483 INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion); in udma_probe()
5487 ud->ddev.copy_align = udma_get_copy_align(ud); in udma_probe()
5489 ret = dma_async_device_register(&ud->ddev); in udma_probe()
5497 ret = of_dma_controller_register(dev->of_node, udma_of_xlate, ud); in udma_probe()
5500 dma_async_device_unregister(&ud->ddev); in udma_probe()
5508 .name = "ti-udma",
5518 .name = "ti-bcdma",
5528 .name = "ti-pktdma",
5537 #include "k3-udma-private.c"