379 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,  in edma_shadow0_write_array()  function
418 		edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit);  in edma_setup_interrupt()
419 		edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit);  in edma_setup_interrupt()
421 		edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit);  in edma_setup_interrupt()
566 		edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit);  in edma_start()
575 		edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);  in edma_start()
576 		edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit);  in edma_start()
589 	edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit);  in edma_stop()
590 	edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit);  in edma_stop()
591 	edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);  in edma_stop()
595 	edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit);  in edma_stop()
613 	edma_shadow0_write_array(echan->ecc, SH_EECR,  in edma_pause()
623 	edma_shadow0_write_array(echan->ecc, SH_EESR,  in edma_resume()
635 	edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit);  in edma_trigger_channel()
650 	edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit);  in edma_clean_channel()
654 	edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);  in edma_clean_channel()
1536 			edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));  in dma_irq_handler()
1642 				edma_shadow0_write_array(ecc, SH_SECR, j,  in dma_ccerr_handler()