262 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)  in stm32_dma_write()  function
445 	stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr);  in stm32_dma_irq_clear()
459 		stm32_dma_write(dmadev, reg, dma_scr);  in stm32_dma_disable_chan()
478 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_stop()
481 	stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);  in stm32_dma_stop()
592 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
593 	stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);  in stm32_dma_start_transfer()
594 	stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);  in stm32_dma_start_transfer()
595 	stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);  in stm32_dma_start_transfer()
596 	stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);  in stm32_dma_start_transfer()
597 	stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);  in stm32_dma_start_transfer()
615 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
633 		stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);  in stm32_dma_configure_next_sg()
638 		stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);  in stm32_dma_configure_next_sg()
673 		stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_handle_chan_paused()
703 	stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr);  in stm32_dma_post_resume_reconfigure()
706 	stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar);  in stm32_dma_post_resume_reconfigure()
709 	stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar);  in stm32_dma_post_resume_reconfigure()
710 	stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar);  in stm32_dma_post_resume_reconfigure()
723 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_post_resume_reconfigure()
730 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_post_resume_reconfigure()
887 		stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar + offset);  in stm32_dma_resume()
889 		stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar);  in stm32_dma_resume()
900 		stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sm1ar + offset);  in stm32_dma_resume()
902 		stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sm0ar + offset);  in stm32_dma_resume()
905 	stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr);  in stm32_dma_resume()
922 	stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);  in stm32_dma_resume()