Lines Matching refs:dma_scr
177 u32 dma_scr; member
387 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
391 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
451 u32 dma_scr, id, reg; in stm32_dma_disable_chan() local
455 dma_scr = stm32_dma_read(dmadev, reg); in stm32_dma_disable_chan()
457 if (dma_scr & STM32_DMA_SCR_EN) { in stm32_dma_disable_chan()
458 dma_scr &= ~STM32_DMA_SCR_EN; in stm32_dma_disable_chan()
459 stm32_dma_write(dmadev, reg, dma_scr); in stm32_dma_disable_chan()
462 dma_scr, !(dma_scr & STM32_DMA_SCR_EN), in stm32_dma_disable_chan()
472 u32 dma_scr, dma_sfcr, status; in stm32_dma_stop() local
476 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
477 dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; in stm32_dma_stop()
478 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
589 reg->dma_scr &= ~STM32_DMA_SCR_TCIE; in stm32_dma_start_transfer()
591 reg->dma_scr &= ~STM32_DMA_SCR_EN; in stm32_dma_start_transfer()
592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
614 reg->dma_scr |= STM32_DMA_SCR_EN; in stm32_dma_start_transfer()
615 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
624 u32 dma_scr, dma_sm0ar, dma_sm1ar, id; in stm32_dma_configure_next_sg() local
627 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); in stm32_dma_configure_next_sg()
631 if (dma_scr & STM32_DMA_SCR_CT) { in stm32_dma_configure_next_sg()
647 u32 dma_scr; in stm32_dma_handle_chan_paused() local
653 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_handle_chan_paused()
661 dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_handle_chan_paused()
663 dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_handle_chan_paused()
665 chan->chan_reg.dma_scr = dma_scr; in stm32_dma_handle_chan_paused()
672 dma_scr &= ~(STM32_DMA_SCR_DBM | STM32_DMA_SCR_CIRC); in stm32_dma_handle_chan_paused()
673 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_handle_chan_paused()
687 u32 dma_scr, status, id; in stm32_dma_post_resume_reconfigure() local
690 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); in stm32_dma_post_resume_reconfigure()
713 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) { in stm32_dma_post_resume_reconfigure()
714 dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_post_resume_reconfigure()
716 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT) in stm32_dma_post_resume_reconfigure()
717 dma_scr &= ~STM32_DMA_SCR_CT; in stm32_dma_post_resume_reconfigure()
719 dma_scr |= STM32_DMA_SCR_CT; in stm32_dma_post_resume_reconfigure()
720 } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) { in stm32_dma_post_resume_reconfigure()
721 dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_post_resume_reconfigure()
723 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_post_resume_reconfigure()
729 dma_scr |= STM32_DMA_SCR_EN; in stm32_dma_post_resume_reconfigure()
730 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_post_resume_reconfigure()
877 offset <<= FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, chan_reg.dma_scr); in stm32_dma_resume()
886 if (chan_reg.dma_scr & STM32_DMA_SCR_PINC) in stm32_dma_resume()
891 if (!(chan_reg.dma_scr & STM32_DMA_SCR_MINC)) in stm32_dma_resume()
899 if ((chan_reg.dma_scr & STM32_DMA_SCR_DBM) && (chan_reg.dma_scr & STM32_DMA_SCR_CT)) in stm32_dma_resume()
911 if (chan_reg.dma_scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM)) in stm32_dma_resume()
912 chan_reg.dma_scr &= ~(STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM); in stm32_dma_resume()
914 if (chan_reg.dma_scr & STM32_DMA_SCR_DBM) in stm32_dma_resume()
921 chan_reg.dma_scr |= STM32_DMA_SCR_EN; in stm32_dma_resume()
922 stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr); in stm32_dma_resume()
940 u32 dma_scr, fifoth; in stm32_dma_set_xfer_param() local
989 dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_MEM_TO_DEV) | in stm32_dma_set_xfer_param()
1046 dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_DEV_TO_MEM) | in stm32_dma_set_xfer_param()
1070 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | in stm32_dma_set_xfer_param()
1073 chan->chan_reg.dma_scr |= dma_scr; in stm32_dma_set_xfer_param()
1111 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
1113 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
1117 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_slave_sg()
1135 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_slave_sg()
1205 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_prep_dma_cyclic()
1207 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_dma_cyclic()
1208 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT; in stm32_dma_prep_dma_cyclic()
1212 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_dma_cyclic()
1224 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_dma_cyclic()
1271 desc->sg_req[i].chan_reg.dma_scr = in stm32_dma_prep_dma_memcpy()
1295 u32 dma_scr, width, ndtr; in stm32_dma_get_remaining_bytes() local
1298 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
1299 width = FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, dma_scr); in stm32_dma_get_remaining_bytes()
1321 u32 dma_scr, dma_smar, id, period_len; in stm32_dma_is_current_sg() local
1324 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); in stm32_dma_is_current_sg()
1327 if (!(dma_scr & STM32_DMA_SCR_DBM)) in stm32_dma_is_current_sg()
1334 if (dma_scr & STM32_DMA_SCR_CT) { in stm32_dma_is_current_sg()
1504 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; in stm32_dma_set_config()
1505 chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line); in stm32_dma_set_config()
1508 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; in stm32_dma_set_config()
1514 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; in stm32_dma_set_config()