57 #define STM32_DMA_SCR(x)		(0x0010 + 0x18 * (x)) /* x = 0..7 */  macro
454 	reg = STM32_DMA_SCR(id);  in stm32_dma_disable_chan()
476 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_stop()
478 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_stop()
533 	u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_dump_reg()
592 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
615 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
627 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_configure_next_sg()
653 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_handle_chan_paused()
673 		stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_handle_chan_paused()
690 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_post_resume_reconfigure()
723 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_post_resume_reconfigure()
730 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_post_resume_reconfigure()
770 	scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_chan_irq()
863 	scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_resume()
922 	stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);  in stm32_dma_resume()
1298 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_get_remaining_bytes()
1324 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_is_current_sg()
1748 		scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));  in stm32_dma_pm_suspend()