Lines Matching +full:0 +full:xfc4
63 #define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
64 #define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0
150 #define FDMA_CMD_STA_OFST 0xFC0
151 #define FDMA_CMD_SET_OFST 0xFC4
152 #define FDMA_CMD_CLR_OFST 0xFC8
153 #define FDMA_CMD_MASK_OFST 0xFCC
154 #define FDMA_CMD_START(ch) (0x1 << (ch << 1))
155 #define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
156 #define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
158 #define FDMA_INT_STA_OFST 0xFD0
159 #define FDMA_INT_STA_CH 0x1
160 #define FDMA_INT_STA_ERR 0x2
162 #define FDMA_INT_SET_OFST 0xFD4
163 #define FDMA_INT_CLR_OFST 0xFD8
164 #define FDMA_INT_MASK_OFST 0xFDC
173 #define FDMA_CH_CMD_OFST 0x200
174 #define FDMA_CH_CMD_STA_MASK GENMASK(1, 0)
175 #define FDMA_CH_CMD_STA_IDLE (0x0)
176 #define FDMA_CH_CMD_STA_START (0x1)
177 #define FDMA_CH_CMD_STA_RUNNING (0x2)
178 #define FDMA_CH_CMD_STA_PAUSED (0x3)
180 #define FDMA_CH_CMD_ERR_INT (0x0 << 2)
181 #define FDMA_CH_CMD_ERR_NAND (0x1 << 2)
182 #define FDMA_CH_CMD_ERR_MCHI (0x2 << 2)
186 + (fchan)->vchan.chan.chan_id * 0x4 \
191 + (fchan)->vchan.chan.chan_id * 0x4 \
195 #define FDMA_REQ_CTRL_OFST 0x240
198 + fchan->dreq_line * 0x04 \
202 #define FDMA_PTRN_OFST 0x800
203 #define FDMA_CNTN_OFST 0x808
204 #define FDMA_SADDRN_OFST 0x80c
205 #define FDMA_DADDRN_OFST 0x810
223 #define FDMA_REQ_CTRL_INIT0 (0x0 << 22)
224 #define FDMA_REQ_CTRL_INIT1 (0x1 << 22)
229 #define FDMA_REQ_CTRL_OPCODE_LD_ST1 (0x0 << 4)
230 #define FDMA_REQ_CTRL_OPCODE_LD_ST2 (0x1 << 4)
231 #define FDMA_REQ_CTRL_OPCODE_LD_ST4 (0x2 << 4)
232 #define FDMA_REQ_CTRL_OPCODE_LD_ST8 (0x3 << 4)
233 #define FDMA_REQ_CTRL_OPCODE_LD_ST16 (0x4 << 4)
234 #define FDMA_REQ_CTRL_OPCODE_LD_ST32 (0x5 << 4)
235 #define FDMA_REQ_CTRL_OPCODE_LD_ST64 (0x6 << 4)
236 #define FDMA_REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0)