Lines Matching full:sdma
3 // drivers/dma/imx-sdma.c
47 /* SDMA registers */
105 * Error bit set in the CCB status field by the SDMA,
146 * 28 Lower WML Event(LWE) SDMA events reg to check for
150 * 29 Higher WML Event(HWE) SDMA events reg to check for
194 * struct sdma_script_start_addrs - SDMA script start pointers
197 * address space of the SDMA engine.
276 * @unused: padding. The SDMA engine expects an array of 128 byte
286 * struct sdma_state_registers - SDMA context for a channel
315 * struct sdma_context_data - sdma context specific to a channel
399 * struct sdma_channel - housekeeping for a SDMA channel
402 * @desc: sdma description including vd and other special member
403 * @sdma: pointer to the SDMA engine for this channel
405 * @direction: transfer type. Needed for setting SDMA script
407 * @peripheral_type: Peripheral type. Needed for setting SDMA script
426 * @data: specific sdma interface structure
441 struct sdma_engine *sdma; member
482 * @magic: "SDMA"
488 * @ram_code_start: offset of SDMA ram image in this firmware image
489 * @ram_code_size: size of SDMA ram image
490 * @script_addrs: Stores the start address of the SDMA scripts
491 * (in SDMA memory space)
509 * ecspi ERR009165 fixed should be done in sdma script
536 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
668 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
669 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
670 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
671 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
672 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
673 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
674 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
675 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
676 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
686 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) in chnenbl_ofs() argument
688 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
695 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership() local
702 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
703 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
704 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
721 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
722 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
723 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
728 static int is_sdma_channel_enabled(struct sdma_engine *sdma, int channel) in is_sdma_channel_enabled() argument
730 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel)); in is_sdma_channel_enabled()
733 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) in sdma_enable_channel() argument
735 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
741 static int sdma_run_channel0(struct sdma_engine *sdma) in sdma_run_channel0() argument
746 sdma_enable_channel(sdma, 0); in sdma_run_channel0()
748 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
751 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
754 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
757 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
763 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, in sdma_load_script() argument
766 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
772 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
776 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
786 ret = sdma_run_channel0(sdma); in sdma_load_script()
788 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
790 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
797 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable() local
800 u32 chnenbl = chnenbl_ofs(sdma, event); in sdma_event_enable()
802 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
804 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
808 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
811 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
817 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable() local
819 u32 chnenbl = chnenbl_ofs(sdma, event); in sdma_event_disable()
822 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
824 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
836 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc() local
847 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
848 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
849 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
889 * SDMA transaction status by the time the client tasklet is in sdma_update_channel_loop()
896 /* Assign buffer ownership to SDMA */ in sdma_update_channel_loop()
904 * SDMA stops cyclic channel when DMA request triggers a channel and no SDMA in sdma_update_channel_loop()
907 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) { in sdma_update_channel_loop()
908 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel); in sdma_update_channel_loop()
909 sdma_enable_channel(sdmac->sdma, sdmac->channel); in sdma_update_channel_loop()
940 struct sdma_engine *sdma = dev_id; in sdma_int_handler() local
943 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
944 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
950 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
973 * sets the pc of SDMA script according to the peripheral type
978 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc() local
994 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
997 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
998 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
1001 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
1002 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
1005 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
1006 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1009 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
1010 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1013 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
1014 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
1017 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1020 if (sdmac->sdma->drvdata->ecspi_fixed) { in sdma_get_pc()
1021 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1023 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; in sdma_get_pc()
1031 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1032 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1035 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
1036 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
1045 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1046 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1049 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1050 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1051 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1055 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1056 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1057 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1060 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
1061 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
1064 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
1067 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
1068 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
1071 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
1074 per_2_emi = sdma->script_addrs->sai_2_mcu_addr; in sdma_get_pc()
1075 emi_2_per = sdma->script_addrs->mcu_2_sai_addr; in sdma_get_pc()
1078 dev_err(sdma->dev, "Unsupported transfer type %d\n", in sdma_get_pc()
1093 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context() local
1096 struct sdma_context_data *context = sdma->context; in sdma_load_context()
1097 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
1113 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1114 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1115 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1116 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1117 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1118 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1120 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1137 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1139 ret = sdma_run_channel0(sdma); in sdma_load_context()
1141 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1154 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel() local
1157 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1167 * According to NXP R&D team a delay of one BD SDMA cost time in sdma_channel_terminate_work()
1169 * bit, to ensure SDMA core has really been stopped after SDMA in sdma_channel_terminate_work()
1215 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p() local
1242 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1243 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1246 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1247 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1337 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority() local
1345 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1350 static int sdma_request_channel0(struct sdma_engine *sdma) in sdma_request_channel0() argument
1354 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1356 if (!sdma->bd0) { in sdma_request_channel0()
1361 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1362 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1364 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1377 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, in sdma_alloc_bd()
1391 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, in sdma_free_bd()
1420 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1449 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1452 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1463 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1465 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1472 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources() local
1487 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1488 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1496 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { in sdma_transfer_init()
1497 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); in sdma_transfer_init()
1539 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy() local
1549 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1579 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1596 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg() local
1608 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1620 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1657 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1680 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic() local
1686 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1699 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1723 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1778 struct sdma_engine *sdma = sdmac->sdma; in sdma_config() local
1785 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n", in sdma_config()
1799 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1804 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1869 static void sdma_add_scripts(struct sdma_engine *sdma, in sdma_add_scripts() argument
1873 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1877 if (!sdma->script_number) in sdma_add_scripts()
1878 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1880 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1882 dev_err(sdma->dev, in sdma_add_scripts()
1883 "SDMA script number %d not match with firmware.\n", in sdma_add_scripts()
1884 sdma->script_number); in sdma_add_scripts()
1888 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1895 * script, both uart ram/rom scripts are present in newer sdma in sdma_add_scripts()
1898 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { in sdma_add_scripts()
1900 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; in sdma_add_scripts()
1902 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; in sdma_add_scripts()
1908 struct sdma_engine *sdma = context; in sdma_load_firmware() local
1914 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1930 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1933 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1936 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1939 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1942 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1949 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1950 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1951 /* download the RAM image for SDMA */ in sdma_load_firmware()
1952 sdma_load_script(sdma, ram_code, in sdma_load_firmware()
1955 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1956 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1958 sdma_add_scripts(sdma, addr); in sdma_load_firmware()
1960 sdma->fw_loaded = true; in sdma_load_firmware()
1962 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1972 static int sdma_event_remap(struct sdma_engine *sdma) in sdma_event_remap() argument
1974 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
1978 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
1988 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
1991 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
1999 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
2007 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2014 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2021 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2036 static int sdma_get_firmware(struct sdma_engine *sdma, in sdma_get_firmware() argument
2042 FW_ACTION_UEVENT, fw_name, sdma->dev, in sdma_get_firmware()
2043 GFP_KERNEL, sdma, sdma_load_firmware); in sdma_get_firmware()
2048 static int sdma_init(struct sdma_engine *sdma) in sdma_init() argument
2053 ret = clk_enable(sdma->clk_ipg); in sdma_init()
2056 ret = clk_enable(sdma->clk_ahb); in sdma_init()
2060 if (sdma->drvdata->check_ratio && in sdma_init()
2061 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
2062 sdma->clk_ratio = 1; in sdma_init()
2064 /* Be sure SDMA has not started yet */ in sdma_init()
2065 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2067 sdma->channel_control = dma_alloc_coherent(sdma->dev, in sdma_init()
2072 if (!sdma->channel_control) { in sdma_init()
2077 sdma->context = (void *)sdma->channel_control + in sdma_init()
2079 sdma->context_phys = ccb_phys + in sdma_init()
2083 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
2084 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
2088 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
2090 ret = sdma_request_channel0(sdma); in sdma_init()
2094 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
2097 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
2100 if (sdma->clk_ratio) in sdma_init()
2101 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2103 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2105 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2108 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
2110 clk_disable(sdma->clk_ipg); in sdma_init()
2111 clk_disable(sdma->clk_ahb); in sdma_init()
2116 clk_disable(sdma->clk_ahb); in sdma_init()
2118 clk_disable(sdma->clk_ipg); in sdma_init()
2119 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
2140 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate() local
2141 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
2173 struct sdma_engine *sdma; in sdma_probe() local
2180 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2181 if (!sdma) in sdma_probe()
2184 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2186 sdma->dev = &pdev->dev; in sdma_probe()
2187 sdma->drvdata = of_device_get_match_data(sdma->dev); in sdma_probe()
2194 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); in sdma_probe()
2195 if (IS_ERR(sdma->regs)) in sdma_probe()
2196 return PTR_ERR(sdma->regs); in sdma_probe()
2198 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2199 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2200 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2202 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2203 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2204 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2206 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2210 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2215 dev_name(&pdev->dev), sdma); in sdma_probe()
2219 sdma->irq = irq; in sdma_probe()
2221 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2222 if (!sdma->script_addrs) { in sdma_probe()
2228 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2229 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2232 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2233 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2234 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2236 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2239 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2241 sdmac->sdma = sdma; in sdma_probe()
2250 * because we need it internally in the SDMA driver. This also means in sdma_probe()
2251 * that channel 0 in dmaengine counting matches sdma channel 1. in sdma_probe()
2254 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2257 ret = sdma_init(sdma); in sdma_probe()
2261 ret = sdma_event_remap(sdma); in sdma_probe()
2265 if (sdma->drvdata->script_addrs) in sdma_probe()
2266 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2268 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2270 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2271 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2272 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2273 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2274 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2275 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2276 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2277 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2278 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2279 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2280 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2281 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2282 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2283 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2284 sdma->dma_device.copy_align = 2; in sdma_probe()
2285 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2287 platform_set_drvdata(pdev, sdma); in sdma_probe()
2289 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2296 ret = of_dma_controller_register(np, sdma_xlate, sdma); in sdma_probe()
2305 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2306 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2316 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2321 ret = sdma_get_firmware(sdma, fw_name); in sdma_probe()
2329 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2331 kfree(sdma->script_addrs); in sdma_probe()
2333 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2335 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2341 struct sdma_engine *sdma = platform_get_drvdata(pdev); in sdma_remove() local
2344 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2345 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2346 kfree(sdma->script_addrs); in sdma_remove()
2347 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2348 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2351 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2363 .name = "imx-sdma",
2373 MODULE_DESCRIPTION("i.MX SDMA driver");
2375 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2378 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");