Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
27 #include <linux/dma-mapping.h>
39 #include <linux/dma/imx-dma.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
45 #include "virt-dma.h"
130 * 0-7 Lower WML Lower watermark level
138 * 0: Source on AIPS
140 * 0: Destination on AIPS
141 * 13-15 --------- MUST BE 0
142 * 16-23 Higher WML HWML
143 * 24-27 N Total number of samples after
154 * 30 --------- MUST BE 0
194 * struct sdma_script_start_addrs - SDMA script start pointers
253 * Mode/Count of data node descriptors - IPCv2
272 * struct sdma_channel_control - Channel control Block
286 * struct sdma_state_registers - SDMA context for a channel
315 * struct sdma_context_data - sdma context specific to a channel
373 * struct sdma_desc - descriptor structor for one transfer
380 * @chn_real_count: the real count updated from bd->mode.count
399 * struct sdma_channel - housekeeping for a SDMA channel
480 * struct sdma_firmware_header - Layout of the firmware image
668 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
669 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
670 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
671 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
672 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
673 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
674 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
675 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
676 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
682 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
688 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
695 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
696 int channel = sdmac->channel; in sdma_config_ownership()
700 return -EINVAL; in sdma_config_ownership()
702 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
703 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
704 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
721 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
722 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
723 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
730 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel)); in is_sdma_channel_enabled()
735 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
739 * sdma_run_channel0 - run a channel and wait till it's done
748 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
751 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
754 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
757 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
766 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
772 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
774 return -ENOMEM; in sdma_load_script()
776 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
778 bd0->mode.command = C0_SETPM; in sdma_load_script()
779 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
780 bd0->mode.count = size / 2; in sdma_load_script()
781 bd0->buffer_addr = buf_phys; in sdma_load_script()
782 bd0->ext_buffer_addr = address; in sdma_load_script()
788 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
790 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
797 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
798 int channel = sdmac->channel; in sdma_event_enable()
802 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
804 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
807 if (sdmac->sw_done) { in sdma_event_enable()
808 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
811 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
817 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
818 int channel = sdmac->channel; in sdma_event_disable()
822 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
824 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
834 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
836 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
837 int channel = sdmac->channel; in sdma_start_desc()
840 sdmac->desc = NULL; in sdma_start_desc()
843 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
845 list_del(&vd->node); in sdma_start_desc()
847 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
848 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
849 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
856 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
859 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
862 while (sdmac->desc) { in sdma_update_channel_loop()
863 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
865 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
867 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
870 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
871 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
872 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
873 error = -EIO; in sdma_update_channel_loop()
877 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
881 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
882 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
883 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
884 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
892 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
893 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
894 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
897 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
900 sdmac->status = old_status; in sdma_update_channel_loop()
907 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) { in sdma_update_channel_loop()
908 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel); in sdma_update_channel_loop()
909 sdma_enable_channel(sdmac->sdma, sdmac->channel); in sdma_update_channel_loop()
919 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
924 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
925 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
927 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
928 error = -EIO; in mxc_sdma_handle_channel_normal()
929 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
933 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
935 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
943 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
944 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
949 int channel = fls(stat) - 1; in sdma_int_handler()
950 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
953 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
954 desc = sdmac->desc; in sdma_int_handler()
956 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
960 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
965 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
978 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
982 * two peripherals or memory-to-memory transfers in sdma_get_pc()
986 sdmac->pc_from_device = 0; in sdma_get_pc()
987 sdmac->pc_to_device = 0; in sdma_get_pc()
988 sdmac->device_to_device = 0; in sdma_get_pc()
989 sdmac->pc_to_pc = 0; in sdma_get_pc()
990 sdmac->is_ram_script = false; in sdma_get_pc()
994 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
997 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
998 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
1001 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
1002 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
1005 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
1006 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1009 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
1010 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1013 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
1014 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
1017 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1020 if (sdmac->sdma->drvdata->ecspi_fixed) { in sdma_get_pc()
1021 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1023 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; in sdma_get_pc()
1024 sdmac->is_ram_script = true; in sdma_get_pc()
1031 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1032 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1035 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
1036 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
1037 sdmac->is_ram_script = true; in sdma_get_pc()
1045 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1046 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1049 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1050 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1051 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1052 sdmac->is_ram_script = true; in sdma_get_pc()
1055 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1056 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1057 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1060 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
1061 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
1064 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
1067 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
1068 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
1071 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
1074 per_2_emi = sdma->script_addrs->sai_2_mcu_addr; in sdma_get_pc()
1075 emi_2_per = sdma->script_addrs->mcu_2_sai_addr; in sdma_get_pc()
1078 dev_err(sdma->dev, "Unsupported transfer type %d\n", in sdma_get_pc()
1080 return -EINVAL; in sdma_get_pc()
1083 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
1084 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
1085 sdmac->device_to_device = per_2_per; in sdma_get_pc()
1086 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
1093 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
1094 int channel = sdmac->channel; in sdma_load_context()
1096 struct sdma_context_data *context = sdma->context; in sdma_load_context()
1097 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
1101 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
1102 load_address = sdmac->pc_from_device; in sdma_load_context()
1103 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
1104 load_address = sdmac->device_to_device; in sdma_load_context()
1105 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
1106 load_address = sdmac->pc_to_pc; in sdma_load_context()
1108 load_address = sdmac->pc_to_device; in sdma_load_context()
1113 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1114 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1115 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1116 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1117 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1118 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1120 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1123 context->channel_state.pc = load_address; in sdma_load_context()
1128 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1129 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1130 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1131 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1132 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1134 bd0->mode.command = C0_SETDM; in sdma_load_context()
1135 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1136 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1137 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1138 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1141 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1154 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1155 int channel = sdmac->channel; in sdma_disable_channel()
1157 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1158 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1174 vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated); in sdma_channel_terminate_work()
1182 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_terminate_all()
1186 if (sdmac->desc) { in sdma_terminate_all()
1187 vchan_terminate_vdesc(&sdmac->desc->vd); in sdma_terminate_all()
1194 vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated); in sdma_terminate_all()
1195 sdmac->desc = NULL; in sdma_terminate_all()
1196 schedule_work(&sdmac->terminate_worker); in sdma_terminate_all()
1199 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_terminate_all()
1208 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1210 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1215 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1217 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1218 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1220 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1221 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1223 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1224 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1226 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1227 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1235 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1237 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1238 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1239 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1242 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1243 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1244 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1246 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1247 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1248 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1250 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1259 if (sdmac->sw_done) in sdma_set_watermarklevel_for_sais()
1260 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE; in sdma_set_watermarklevel_for_sais()
1262 if (sdmac->direction == DMA_DEV_TO_MEM) { in sdma_set_watermarklevel_for_sais()
1263 n_fifos = sdmac->n_fifos_src; in sdma_set_watermarklevel_for_sais()
1264 stride_fifos = sdmac->stride_fifos_src; in sdma_set_watermarklevel_for_sais()
1266 n_fifos = sdmac->n_fifos_dst; in sdma_set_watermarklevel_for_sais()
1267 stride_fifos = sdmac->stride_fifos_dst; in sdma_set_watermarklevel_for_sais()
1270 words_per_fifo = sdmac->words_per_fifo; in sdma_set_watermarklevel_for_sais()
1272 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1274 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1277 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1278 FIELD_PREP(SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO, (words_per_fifo - 1)); in sdma_set_watermarklevel_for_sais()
1288 sdmac->event_mask[0] = 0; in sdma_config_channel()
1289 sdmac->event_mask[1] = 0; in sdma_config_channel()
1290 sdmac->shp_addr = 0; in sdma_config_channel()
1291 sdmac->per_addr = 0; in sdma_config_channel()
1293 switch (sdmac->peripheral_type) { in sdma_config_channel()
1305 ret = sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1309 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1310 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1312 if (sdmac->event_id1) { in sdma_config_channel()
1313 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1314 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1317 if (sdmac->peripheral_type == in sdma_config_channel()
1321 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1325 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1326 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1328 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1337 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1338 int channel = sdmac->channel; in sdma_set_channel_priority()
1342 return -EINVAL; in sdma_set_channel_priority()
1345 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1352 int ret = -EBUSY; in sdma_request_channel0()
1354 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1356 if (!sdma->bd0) { in sdma_request_channel0()
1357 ret = -ENOMEM; in sdma_request_channel0()
1361 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1362 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1364 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1374 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1377 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, in sdma_alloc_bd()
1378 &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1379 if (!desc->bd) { in sdma_alloc_bd()
1380 ret = -ENOMEM; in sdma_alloc_bd()
1389 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1391 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, in sdma_free_bd()
1392 desc->bd_phys); in sdma_free_bd()
1406 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1411 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1413 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1420 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1432 switch (data->priority) { in sdma_alloc_chan_resources()
1445 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1446 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1447 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1449 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1452 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1463 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1465 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1472 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1478 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1479 if (sdmac->event_id1) in sdma_free_chan_resources()
1480 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1482 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1483 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1487 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1488 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1496 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { in sdma_transfer_init()
1497 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); in sdma_transfer_init()
1505 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1506 sdmac->direction = direction; in sdma_transfer_init()
1507 sdmac->flags = 0; in sdma_transfer_init()
1509 desc->chn_count = 0; in sdma_transfer_init()
1510 desc->chn_real_count = 0; in sdma_transfer_init()
1511 desc->buf_tail = 0; in sdma_transfer_init()
1512 desc->buf_ptail = 0; in sdma_transfer_init()
1513 desc->sdmac = sdmac; in sdma_transfer_init()
1514 desc->num_bd = bds; in sdma_transfer_init()
1539 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1540 int channel = sdmac->channel; in sdma_prep_memcpy()
1549 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1559 bd = &desc->bd[i]; in sdma_prep_memcpy()
1560 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1561 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1562 bd->mode.count = count; in sdma_prep_memcpy()
1563 desc->chn_count += count; in sdma_prep_memcpy()
1564 bd->mode.command = 0; in sdma_prep_memcpy()
1568 len -= count; in sdma_prep_memcpy()
1579 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1580 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1584 bd->mode.status = param; in sdma_prep_memcpy()
1587 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1596 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1598 int channel = sdmac->channel; in sdma_prep_slave_sg()
1602 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1608 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1612 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1615 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1620 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1625 bd->mode.count = count; in sdma_prep_slave_sg()
1626 desc->chn_count += count; in sdma_prep_slave_sg()
1628 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1631 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1633 bd->mode.command = 0; in sdma_prep_slave_sg()
1634 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1638 bd->mode.command = 2; in sdma_prep_slave_sg()
1639 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1643 bd->mode.command = 1; in sdma_prep_slave_sg()
1657 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1658 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1662 bd->mode.status = param; in sdma_prep_slave_sg()
1665 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1670 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1680 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1682 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1686 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1688 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1694 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1696 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1699 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1705 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1708 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1710 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1712 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1714 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1715 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1717 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1723 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1728 bd->mode.status = param; in sdma_prep_dma_cyclic()
1736 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1741 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1752 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1753 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1754 dmaengine_cfg->src_addr_width; in sdma_config_write()
1755 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1757 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1758 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1759 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1761 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1763 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1765 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1766 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1767 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1768 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1770 sdmac->direction = direction; in sdma_config_write()
1778 struct sdma_engine *sdma = sdmac->sdma; in sdma_config()
1780 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1782 if (dmaengine_cfg->peripheral_config) { in sdma_config()
1783 struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config; in sdma_config()
1784 if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) { in sdma_config()
1785 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n", in sdma_config()
1786 dmaengine_cfg->peripheral_size, in sdma_config()
1788 return -EINVAL; in sdma_config()
1790 sdmac->n_fifos_src = sdmacfg->n_fifos_src; in sdma_config()
1791 sdmac->n_fifos_dst = sdmacfg->n_fifos_dst; in sdma_config()
1792 sdmac->stride_fifos_src = sdmacfg->stride_fifos_src; in sdma_config()
1793 sdmac->stride_fifos_dst = sdmacfg->stride_fifos_dst; in sdma_config()
1794 sdmac->words_per_fifo = sdmacfg->words_per_fifo; in sdma_config()
1795 sdmac->sw_done = sdmacfg->sw_done; in sdma_config()
1799 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1800 return -EINVAL; in sdma_config()
1801 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1803 if (sdmac->event_id1) { in sdma_config()
1804 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1805 return -EINVAL; in sdma_config()
1806 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1827 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1829 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1831 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1832 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) in sdma_tx_status()
1833 desc = sdmac->desc; in sdma_tx_status()
1836 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1837 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1838 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1840 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1845 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1847 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1850 return sdmac->status; in sdma_tx_status()
1858 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1859 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1861 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1873 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1877 if (!sdma->script_number) in sdma_add_scripts()
1878 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1880 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1882 dev_err(sdma->dev, in sdma_add_scripts()
1884 sdma->script_number); in sdma_add_scripts()
1888 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1898 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { in sdma_add_scripts()
1899 if (addr->uart_2_mcu_rom_addr) in sdma_add_scripts()
1900 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; in sdma_add_scripts()
1901 if (addr->uartsh_2_mcu_rom_addr) in sdma_add_scripts()
1902 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; in sdma_add_scripts()
1914 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1919 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1922 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1924 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1926 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1928 switch (header->version_major) { in sdma_load_firmware()
1930 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1933 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1936 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1939 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1942 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1946 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
1947 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
1949 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1950 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1953 header->ram_code_size, in sdma_load_firmware()
1954 addr->ram_code_start_addr); in sdma_load_firmware()
1955 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1956 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1960 sdma->fw_loaded = true; in sdma_load_firmware()
1962 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1963 header->version_major, in sdma_load_firmware()
1964 header->version_minor); in sdma_load_firmware()
1974 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
1978 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
1986 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
1988 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
1991 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
1993 ret = -EINVAL; in sdma_event_remap()
1999 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
2007 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2014 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2021 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2042 FW_ACTION_UEVENT, fw_name, sdma->dev, in sdma_get_firmware()
2053 ret = clk_enable(sdma->clk_ipg); in sdma_init()
2056 ret = clk_enable(sdma->clk_ahb); in sdma_init()
2060 if (sdma->drvdata->check_ratio && in sdma_init()
2061 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
2062 sdma->clk_ratio = 1; in sdma_init()
2065 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2067 sdma->channel_control = dma_alloc_coherent(sdma->dev, in sdma_init()
2072 if (!sdma->channel_control) { in sdma_init()
2073 ret = -ENOMEM; in sdma_init()
2077 sdma->context = (void *)sdma->channel_control + in sdma_init()
2079 sdma->context_phys = ccb_phys + in sdma_init()
2083 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
2084 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
2088 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
2094 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
2097 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
2100 if (sdma->clk_ratio) in sdma_init()
2101 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2103 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2105 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2108 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
2110 clk_disable(sdma->clk_ipg); in sdma_init()
2111 clk_disable(sdma->clk_ahb); in sdma_init()
2116 clk_disable(sdma->clk_ahb); in sdma_init()
2118 clk_disable(sdma->clk_ipg); in sdma_init()
2119 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
2131 sdmac->data = *data; in sdma_filter_fn()
2132 chan->private = &sdmac->data; in sdma_filter_fn()
2140 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
2141 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
2144 if (dma_spec->args_count != 3) in sdma_xlate()
2147 data.dma_request = dma_spec->args[0]; in sdma_xlate()
2148 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
2149 data.priority = dma_spec->args[2]; in sdma_xlate()
2153 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
2155 * be set to sdmac->event_id1. in sdma_xlate()
2160 ofdma->of_node); in sdma_xlate()
2165 struct device_node *np = pdev->dev.of_node; in sdma_probe()
2176 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
2180 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2182 return -ENOMEM; in sdma_probe()
2184 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2186 sdma->dev = &pdev->dev; in sdma_probe()
2187 sdma->drvdata = of_device_get_match_data(sdma->dev); in sdma_probe()
2194 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); in sdma_probe()
2195 if (IS_ERR(sdma->regs)) in sdma_probe()
2196 return PTR_ERR(sdma->regs); in sdma_probe()
2198 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2199 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2200 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2202 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2203 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2204 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2206 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2210 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2214 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, in sdma_probe()
2215 dev_name(&pdev->dev), sdma); in sdma_probe()
2219 sdma->irq = irq; in sdma_probe()
2221 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2222 if (!sdma->script_addrs) { in sdma_probe()
2223 ret = -ENOMEM; in sdma_probe()
2228 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2229 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2230 saddr_arr[i] = -EINVAL; in sdma_probe()
2232 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2233 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2234 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2236 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2239 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2241 sdmac->sdma = sdma; in sdma_probe()
2243 sdmac->channel = i; in sdma_probe()
2244 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2245 INIT_LIST_HEAD(&sdmac->terminated); in sdma_probe()
2246 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2254 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2265 if (sdma->drvdata->script_addrs) in sdma_probe()
2266 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2268 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2270 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2271 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2272 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2273 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2274 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2275 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2276 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2277 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2278 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2279 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2280 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2281 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2282 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2283 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2284 sdma->dma_device.copy_align = 2; in sdma_probe()
2285 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2289 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2291 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2298 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2302 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2305 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2306 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2316 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2319 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2323 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2329 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2331 kfree(sdma->script_addrs); in sdma_probe()
2333 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2335 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2344 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2345 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2346 kfree(sdma->script_addrs); in sdma_remove()
2347 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2348 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2351 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2353 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2354 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2363 .name = "imx-sdma",
2375 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2378 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");