1 /* SPDX-License-Identifier: GPL-2.0 */
21 #define GET_IDXD_VER_MAJOR(x)		(((x) & IDXD_VER_MAJOR_MASK) >> 4)
36 		u64 max_batch_shift:4;
41 	u64 bits;  member
49 		u64 wqcfg_size:4;
60 	u64 bits;  member
74 	u64 bits;  member
83 	u64 bits;  member
92 	u64 bits[4];  member
109 	u64 bits[2];  member
118 		u32 rsvd:4;
122 	u32 bits;  member
132 	u32 bits;  member
142 	u32 bits;  member
175 	u32 bits;  member
205 	u32 bits;  member
266 		u64 rsvd3:4;
276 	u64 bits[4];  member
287 	u32 bits;  member
297 		u64 rsvd2:4;
299 		u64 rsvd3:4;
305 	u64 bits;  member
309 	u64 wqs[4];
316 		/* bytes 0-3 */
320 		/* bytes 4-7 */
324 		/* bytes 8-11 */
329 		u32 priority:4;
335 		/* bytes 12-15 */
337 		u32 max_batch_shift:4;
340 		/* bytes 16-19 */
345 		/* bytes 20-23 */
350 		/* bytes 24-27 */
357 		/* bytes 28-31 */
360 		/* bytes 32-63 */
361 		u64 op_config[4];
363 	u32 bits[16];  member
374  * idxd - struct idxd *
375  * n - wq id
376  * ofs - the index of the 32b dword for the config register
380  * Each register is 32bits. The ofs gives us the number of register to access.
385 	(__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs);	\
388 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
391 #define GRPWQCFG_STRIDES	4
395  * idxd - struct idxd *
396  * n - wq id
397  * ofs - the index of the 32b dword for the config register
401  * Each register is 32bits. The ofs gives us the number of register to access.
403 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
405 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32)
406 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40)
415 		u64 num_event_category:4;
425 	u64 bits;  member
434 	u64 bits;  member
440 			u32 event_category:4;
453 			u32 num_events:4;
479 		u64 event_category:4;
482 		u64 rsvd3:4;
499 		u64 event_cat:4;
509 		u64 pg_sz:4;