Lines Matching +full:address +full:- +full:width
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
108 u32 mr; /* 0x00 - Mode Register */
109 u32 sr; /* 0x04 - Status Register */
110 u64 cdar; /* 0x08 - Current descriptor address register */
111 u64 sar; /* 0x10 - Source Address Register */
112 u64 dar; /* 0x18 - Destination Address Register */
113 u32 bcr; /* 0x20 - Byte Count Register */
114 u64 ndar; /* 0x24 - Next Descriptor Address Register */
129 /* Define macros for fsldma_chan->feature property */
247 #define FSL_DMA_IN(fsl_dma, addr, width) \ argument
248 (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \
249 fsl_ioread##width##be(addr) : fsl_ioread##width(addr))
251 #define FSL_DMA_OUT(fsl_dma, addr, val, width) \ argument
252 (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \
253 fsl_iowrite##width##be(val, addr) : fsl_iowrite \
254 ##width(val, addr))
256 #define DMA_TO_CPU(fsl_chan, d, width) \ argument
257 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
258 be##width##_to_cpu((__force __be##width)(v##width)d) : \
259 le##width##_to_cpu((__force __le##width)(v##width)d))
260 #define CPU_TO_DMA(fsl_chan, c, width) \ argument
261 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
262 (__force v##width)cpu_to_be##width(c) : \
263 (__force v##width)cpu_to_le##width(c))