Lines Matching refs:fsl_edma
33 struct fsl_edma_engine *fsl_edma = dev_id; in fsl_edma_tx_handler() local
35 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
38 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
42 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
44 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); in fsl_edma_tx_handler()
46 fsl_chan = &fsl_edma->chans[ch]; in fsl_edma_tx_handler()
77 struct fsl_edma_engine *fsl_edma = dev_id; in fsl_edma_err_handler() local
79 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_err_handler()
81 err = edma_readl(fsl_edma, regs->errl); in fsl_edma_err_handler()
85 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_err_handler()
87 fsl_edma_disable_request(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
88 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); in fsl_edma_err_handler()
89 fsl_edma->chans[ch].status = DMA_ERROR; in fsl_edma_err_handler()
90 fsl_edma->chans[ch].idle = true; in fsl_edma_err_handler()
107 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma_xlate() local
110 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; in fsl_edma_xlate()
111 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; in fsl_edma_xlate()
116 mutex_lock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
117 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
128 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
133 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
138 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) in fsl_edma_irq_init() argument
142 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
143 if (fsl_edma->txirq < 0) in fsl_edma_irq_init()
144 return fsl_edma->txirq; in fsl_edma_irq_init()
146 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
147 if (fsl_edma->errirq < 0) in fsl_edma_irq_init()
148 return fsl_edma->errirq; in fsl_edma_irq_init()
150 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_init()
151 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
152 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
158 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
159 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); in fsl_edma_irq_init()
165 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma_irq_init()
166 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); in fsl_edma_irq_init()
178 struct fsl_edma_engine *fsl_edma) in fsl_edma2_irq_init() argument
200 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); in fsl_edma2_irq_init()
206 0, "eDMA2-ERR", fsl_edma); in fsl_edma2_irq_init()
210 fsl_edma->chans[i].chan_name, in fsl_edma2_irq_init()
211 fsl_edma); in fsl_edma2_irq_init()
220 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) in fsl_edma_irq_exit() argument
222 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_exit()
223 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
225 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
226 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); in fsl_edma_irq_exit()
230 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) in fsl_disable_clocks() argument
235 clk_disable_unprepare(fsl_edma->muxclk[i]); in fsl_disable_clocks()
271 struct fsl_edma_engine *fsl_edma; in fsl_edma_probe() local
292 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans; in fsl_edma_probe()
293 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); in fsl_edma_probe()
294 if (!fsl_edma) in fsl_edma_probe()
297 fsl_edma->drvdata = drvdata; in fsl_edma_probe()
298 fsl_edma->n_chans = chans; in fsl_edma_probe()
299 mutex_init(&fsl_edma->fsl_edma_mutex); in fsl_edma_probe()
302 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
303 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
304 return PTR_ERR(fsl_edma->membase); in fsl_edma_probe()
306 fsl_edma_setup_regs(fsl_edma); in fsl_edma_probe()
307 regs = &fsl_edma->regs; in fsl_edma_probe()
310 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); in fsl_edma_probe()
311 if (IS_ERR(fsl_edma->dmaclk)) { in fsl_edma_probe()
313 return PTR_ERR(fsl_edma->dmaclk); in fsl_edma_probe()
316 ret = clk_prepare_enable(fsl_edma->dmaclk); in fsl_edma_probe()
323 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { in fsl_edma_probe()
327 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
328 if (IS_ERR(fsl_edma->muxbase[i])) { in fsl_edma_probe()
330 fsl_disable_clocks(fsl_edma, i); in fsl_edma_probe()
331 return PTR_ERR(fsl_edma->muxbase[i]); in fsl_edma_probe()
335 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); in fsl_edma_probe()
336 if (IS_ERR(fsl_edma->muxclk[i])) { in fsl_edma_probe()
339 fsl_disable_clocks(fsl_edma, i); in fsl_edma_probe()
340 return PTR_ERR(fsl_edma->muxclk[i]); in fsl_edma_probe()
343 ret = clk_prepare_enable(fsl_edma->muxclk[i]); in fsl_edma_probe()
346 fsl_disable_clocks(fsl_edma, i); in fsl_edma_probe()
350 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); in fsl_edma_probe()
352 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); in fsl_edma_probe()
353 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_probe()
354 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma_probe()
356 fsl_chan->edma = fsl_edma; in fsl_edma_probe()
362 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); in fsl_edma_probe()
364 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); in fsl_edma_probe()
368 edma_writel(fsl_edma, ~0, regs->intl); in fsl_edma_probe()
369 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); in fsl_edma_probe()
373 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
374 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
375 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
376 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
378 fsl_edma->dma_dev.dev = &pdev->dev; in fsl_edma_probe()
379 fsl_edma->dma_dev.device_alloc_chan_resources in fsl_edma_probe()
381 fsl_edma->dma_dev.device_free_chan_resources in fsl_edma_probe()
383 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; in fsl_edma_probe()
384 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; in fsl_edma_probe()
385 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; in fsl_edma_probe()
386 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; in fsl_edma_probe()
387 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; in fsl_edma_probe()
388 fsl_edma->dma_dev.device_pause = fsl_edma_pause; in fsl_edma_probe()
389 fsl_edma->dma_dev.device_resume = fsl_edma_resume; in fsl_edma_probe()
390 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; in fsl_edma_probe()
391 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; in fsl_edma_probe()
392 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; in fsl_edma_probe()
394 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
395 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
396 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsl_edma_probe()
398 fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES; in fsl_edma_probe()
400 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); in fsl_edma_probe()
402 platform_set_drvdata(pdev, fsl_edma); in fsl_edma_probe()
404 ret = dma_async_device_register(&fsl_edma->dma_dev); in fsl_edma_probe()
408 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_probe()
412 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma); in fsl_edma_probe()
416 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_probe()
417 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_probe()
422 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_probe()
430 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); in fsl_edma_remove() local
432 fsl_edma_irq_exit(pdev, fsl_edma); in fsl_edma_remove()
433 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); in fsl_edma_remove()
435 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_remove()
436 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_remove()
443 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); in fsl_edma_suspend_late() local
448 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_suspend_late()
449 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_suspend_late()
467 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); in fsl_edma_resume_early() local
469 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_resume_early()
472 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_resume_early()
473 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_resume_early()
475 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); in fsl_edma_resume_early()
480 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_resume_early()