1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
11 #include "dw-edma-core.h"
12 #include "dw-edma-v0-core.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-v0-debugfs.h"
28 	return dw->chip->reg_base;  in __dw_regs()
31 #define SET_32(dw, name, value)				\  argument
32 	writel(value, &(__dw_regs(dw)->name))
34 #define GET_32(dw, name)				\  argument
35 	readl(&(__dw_regs(dw)->name))
37 #define SET_RW_32(dw, dir, name, value)			\  argument
40 			SET_32(dw, wr_##name, value);	\
42 			SET_32(dw, rd_##name, value);	\
45 #define GET_RW_32(dw, dir, name)			\  argument
47 	  ? GET_32(dw, wr_##name)			\
48 	  : GET_32(dw, rd_##name))
50 #define SET_BOTH_32(dw, name, value)			\  argument
52 		SET_32(dw, wr_##name, value);		\
53 		SET_32(dw, rd_##name, value);		\
58 #define SET_64(dw, name, value)				\  argument
59 	writeq(value, &(__dw_regs(dw)->name))
61 #define GET_64(dw, name)				\  argument
62 	readq(&(__dw_regs(dw)->name))
64 #define SET_RW_64(dw, dir, name, value)			\  argument
67 			SET_64(dw, wr_##name, value);	\
69 			SET_64(dw, rd_##name, value);	\
72 #define GET_RW_64(dw, dir, name)			\  argument
74 	  ? GET_64(dw, wr_##name)			\
75 	  : GET_64(dw, rd_##name))
77 #define SET_BOTH_64(dw, name, value)			\  argument
79 		SET_64(dw, wr_##name, value);		\
80 		SET_64(dw, rd_##name, value);		\
85 #define SET_COMPAT(dw, name, value)			\  argument
86 	writel(value, &(__dw_regs(dw)->type.unroll.name))
88 #define SET_RW_COMPAT(dw, dir, name, value)		\  argument
91 			SET_COMPAT(dw, wr_##name, value); \
93 			SET_COMPAT(dw, rd_##name, value); \
99 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)  in __dw_ch_regs()
100 		return &(__dw_regs(dw)->type.legacy.ch);  in __dw_ch_regs()
103 		return &__dw_regs(dw)->type.unroll.ch[ch].wr;  in __dw_ch_regs()
105 	return &__dw_regs(dw)->type.unroll.ch[ch].rd;  in __dw_ch_regs()
111 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {  in writel_ch()
115 		raw_spin_lock_irqsave(&dw->lock, flags);  in writel_ch()
122 		       &(__dw_regs(dw)->type.legacy.viewport_sel));  in writel_ch()
125 		raw_spin_unlock_irqrestore(&dw->lock, flags);  in writel_ch()
136 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {  in readl_ch()
140 		raw_spin_lock_irqsave(&dw->lock, flags);  in readl_ch()
147 		       &(__dw_regs(dw)->type.legacy.viewport_sel));  in readl_ch()
150 		raw_spin_unlock_irqrestore(&dw->lock, flags);  in readl_ch()
158 #define SET_CH_32(dw, dir, ch, name, value) \  argument
159 	writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
161 #define GET_CH_32(dw, dir, ch, name) \  argument
162 	readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
172 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {  in writeq_ch()
176 		raw_spin_lock_irqsave(&dw->lock, flags);  in writeq_ch()
183 		       &(__dw_regs(dw)->type.legacy.viewport_sel));  in writeq_ch()
186 		raw_spin_unlock_irqrestore(&dw->lock, flags);  in writeq_ch()
197 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {  in readq_ch()
201 		raw_spin_lock_irqsave(&dw->lock, flags);  in readq_ch()
208 		       &(__dw_regs(dw)->type.legacy.viewport_sel));  in readq_ch()
211 		raw_spin_unlock_irqrestore(&dw->lock, flags);  in readq_ch()
219 #define SET_CH_64(dw, dir, ch, name, value) \  argument
220 	writeq_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
222 #define GET_CH_64(dw, dir, ch, name) \  argument
223 	readq_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
257 enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)  in dw_edma_v0_core_ch_status()  argument
259 	struct dw_edma *dw = chan->dw;  in dw_edma_v0_core_ch_status()
263 			GET_CH_32(dw, chan->dir, chan->id, ch_control1));  in dw_edma_v0_core_ch_status()
273 void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)  in dw_edma_v0_core_clear_done_int()  argument
275 	struct dw_edma *dw = chan->dw;  in dw_edma_v0_core_clear_done_int()
277 	SET_RW_32(dw, chan->dir, int_clear,  in dw_edma_v0_core_clear_done_int()
278 		  FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)));  in dw_edma_v0_core_clear_done_int()
281 void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)  in dw_edma_v0_core_clear_abort_int()  argument
283 	struct dw_edma *dw = chan->dw;  in dw_edma_v0_core_clear_abort_int()
285 	SET_RW_32(dw, chan->dir, int_clear,  in dw_edma_v0_core_clear_abort_int()
286 		  FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)));  in dw_edma_v0_core_clear_abort_int()
304 	struct dw_edma_chan *chan = chunk->chan;  in dw_edma_v0_core_write_chunk()  local
310 	lli = chunk->ll_region.vaddr;  in dw_edma_v0_core_write_chunk()
312 	if (chunk->cb)  in dw_edma_v0_core_write_chunk()
315 	j = chunk->bursts_alloc;  in dw_edma_v0_core_write_chunk()
316 	list_for_each_entry(child, &chunk->burst->list, list) {  in dw_edma_v0_core_write_chunk()
317 		j--;  in dw_edma_v0_core_write_chunk()
320 			if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))  in dw_edma_v0_core_write_chunk()
326 		SET_LL_32(&lli[i].transfer_size, child->sz);  in dw_edma_v0_core_write_chunk()
329 			SET_LL_64(&lli[i].sar.reg, child->sar);  in dw_edma_v0_core_write_chunk()
331 			SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar));  in dw_edma_v0_core_write_chunk()
332 			SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar));  in dw_edma_v0_core_write_chunk()
336 			SET_LL_64(&lli[i].dar.reg, child->dar);  in dw_edma_v0_core_write_chunk()
338 			SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar));  in dw_edma_v0_core_write_chunk()
339 			SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar));  in dw_edma_v0_core_write_chunk()
346 	if (!chunk->cb)  in dw_edma_v0_core_write_chunk()
350 	SET_LL_32(&llp->control, control);  in dw_edma_v0_core_write_chunk()
353 		SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);  in dw_edma_v0_core_write_chunk()
355 		SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr));  in dw_edma_v0_core_write_chunk()
356 		SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr));  in dw_edma_v0_core_write_chunk()
362 	struct dw_edma_chan *chan = chunk->chan;  in dw_edma_v0_core_start()  local
363 	struct dw_edma *dw = chan->dw;  in dw_edma_v0_core_start()
370 		SET_RW_32(dw, chan->dir, engine_en, BIT(0));  in dw_edma_v0_core_start()
371 		if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) {  in dw_edma_v0_core_start()
372 			switch (chan->id) {  in dw_edma_v0_core_start()
374 				SET_RW_COMPAT(dw, chan->dir, ch0_pwr_en,  in dw_edma_v0_core_start()
378 				SET_RW_COMPAT(dw, chan->dir, ch1_pwr_en,  in dw_edma_v0_core_start()
382 				SET_RW_COMPAT(dw, chan->dir, ch2_pwr_en,  in dw_edma_v0_core_start()
386 				SET_RW_COMPAT(dw, chan->dir, ch3_pwr_en,  in dw_edma_v0_core_start()
390 				SET_RW_COMPAT(dw, chan->dir, ch4_pwr_en,  in dw_edma_v0_core_start()
394 				SET_RW_COMPAT(dw, chan->dir, ch5_pwr_en,  in dw_edma_v0_core_start()
398 				SET_RW_COMPAT(dw, chan->dir, ch6_pwr_en,  in dw_edma_v0_core_start()
402 				SET_RW_COMPAT(dw, chan->dir, ch7_pwr_en,  in dw_edma_v0_core_start()
407 		/* Interrupt unmask - done, abort */  in dw_edma_v0_core_start()
408 		tmp = GET_RW_32(dw, chan->dir, int_mask);  in dw_edma_v0_core_start()
409 		tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));  in dw_edma_v0_core_start()
410 		tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));  in dw_edma_v0_core_start()
411 		SET_RW_32(dw, chan->dir, int_mask, tmp);  in dw_edma_v0_core_start()
413 		tmp = GET_RW_32(dw, chan->dir, linked_list_err_en);  in dw_edma_v0_core_start()
414 		tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id));  in dw_edma_v0_core_start()
415 		SET_RW_32(dw, chan->dir, linked_list_err_en, tmp);  in dw_edma_v0_core_start()
417 		SET_CH_32(dw, chan->dir, chan->id, ch_control1,  in dw_edma_v0_core_start()
420 		/* llp is not aligned on 64bit -> keep 32bit accesses */  in dw_edma_v0_core_start()
421 		SET_CH_32(dw, chan->dir, chan->id, llp.lsb,  in dw_edma_v0_core_start()
422 			  lower_32_bits(chunk->ll_region.paddr));  in dw_edma_v0_core_start()
423 		SET_CH_32(dw, chan->dir, chan->id, llp.msb,  in dw_edma_v0_core_start()
424 			  upper_32_bits(chunk->ll_region.paddr));  in dw_edma_v0_core_start()
427 	SET_RW_32(dw, chan->dir, doorbell,  in dw_edma_v0_core_start()
428 		  FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));  in dw_edma_v0_core_start()
431 int dw_edma_v0_core_device_config(struct dw_edma_chan *chan)  in dw_edma_v0_core_device_config()  argument
433 	struct dw_edma *dw = chan->dw;  in dw_edma_v0_core_device_config()
436 	/* MSI done addr - low, high */  in dw_edma_v0_core_device_config()
437 	SET_RW_32(dw, chan->dir, done_imwr.lsb, chan->msi.address_lo);  in dw_edma_v0_core_device_config()
438 	SET_RW_32(dw, chan->dir, done_imwr.msb, chan->msi.address_hi);  in dw_edma_v0_core_device_config()
439 	/* MSI abort addr - low, high */  in dw_edma_v0_core_device_config()
440 	SET_RW_32(dw, chan->dir, abort_imwr.lsb, chan->msi.address_lo);  in dw_edma_v0_core_device_config()
441 	SET_RW_32(dw, chan->dir, abort_imwr.msb, chan->msi.address_hi);  in dw_edma_v0_core_device_config()
442 	/* MSI data - low, high */  in dw_edma_v0_core_device_config()
443 	switch (chan->id) {  in dw_edma_v0_core_device_config()
446 		tmp = GET_RW_32(dw, chan->dir, ch01_imwr_data);  in dw_edma_v0_core_device_config()
451 		tmp = GET_RW_32(dw, chan->dir, ch23_imwr_data);  in dw_edma_v0_core_device_config()
456 		tmp = GET_RW_32(dw, chan->dir, ch45_imwr_data);  in dw_edma_v0_core_device_config()
461 		tmp = GET_RW_32(dw, chan->dir, ch67_imwr_data);  in dw_edma_v0_core_device_config()
465 	if (chan->id & BIT(0)) {  in dw_edma_v0_core_device_config()
469 				  chan->msi.data);  in dw_edma_v0_core_device_config()
474 				  chan->msi.data);  in dw_edma_v0_core_device_config()
477 	switch (chan->id) {  in dw_edma_v0_core_device_config()
480 		SET_RW_32(dw, chan->dir, ch01_imwr_data, tmp);  in dw_edma_v0_core_device_config()
485 		SET_RW_32(dw, chan->dir, ch23_imwr_data, tmp);  in dw_edma_v0_core_device_config()
490 		SET_RW_32(dw, chan->dir, ch45_imwr_data, tmp);  in dw_edma_v0_core_device_config()
495 		SET_RW_32(dw, chan->dir, ch67_imwr_data, tmp);  in dw_edma_v0_core_device_config()