1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Header file for the Atmel AHB DMA Controller driver
14 #define		AT_DMA_IF_BIGEND(i)	(0x1 << (i))	/* AHB-Lite Interface i in Big-endian mode */
79 #define	ATC_DSCR_IF(i)		(0x3 & (i))	/* Dsc feched via AHB-Lite Interface i */
118 #define	ATC_SIF(i)		(0x3 & (i))	/* Src tx done via AHB-Lite Interface i */
119 #define	ATC_DIF(i)		((0x3 & (i)) <<  4)	/* Dst tx done via AHB-Lite Interface i */
124 #define	ATC_SRC_PIP		(0x1 <<  8)	/* Source Picture-in-Picture enabled */
125 #define	ATC_DST_PIP		(0x1 << 12)	/* Destination Picture-in-Picture enabled */
129 #define		ATC_FC_MEM2MEM		(0x0 << 21)	/* Mem-to-Mem (DMA) */
130 #define		ATC_FC_MEM2PER		(0x1 << 21)	/* Mem-to-Periph (DMA) */
131 #define		ATC_FC_PER2MEM		(0x2 << 21)	/* Periph-to-Mem (DMA) */
132 #define		ATC_FC_PER2PER		(0x3 << 21)	/* Periph-to-Periph (DMA) */
133 #define		ATC_FC_PER2MEM_PER	(0x4 << 21)	/* Periph-to-Mem (Peripheral) */
134 #define		ATC_FC_MEM2PER_PER	(0x5 << 21)	/* Mem-to-Periph (Peripheral) */
135 #define		ATC_FC_PER2PER_SRCPER	(0x6 << 21)	/* Periph-to-Periph (Src Peripheral) */
136 #define		ATC_FC_PER2PER_DSTPER	(0x7 << 21)	/* Periph-to-Periph (Dst Peripheral) */
184 /*--  descriptors  -----------------------------------------------------*/
186 /* LLI == Linked List Item; aka DMA buffer descriptor */
199  * struct at_desc - software descriptor
235 /*--  Channels  --------------------------------------------------------*/
238  * atc_status - information bits stored in channel status flag
249  * struct at_dma_chan - internal representation of an Atmel HDMAC channel
291 	__raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
294 	__raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
303  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
307 static inline void convert_burst(u32 *maxburst)  in convert_burst()  argument
309 	if (*maxburst > 1)  in convert_burst()
310 		*maxburst = fls(*maxburst) - 2;  in convert_burst()
312 		*maxburst = 0;  in convert_burst()
317  * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
332 /*--  Controller  ------------------------------------------------------*/
335  * struct at_dma - internal representation of an Atmel HDMA Controller
337  * @atdma_devtype: identifier of DMA controller compatibility
339  * @clk: dma controller clock
342  * @dma_desc_pool: base of DMA descriptor region (DMA address)
360 	__raw_readl((atdma)->regs + AT_DMA_##name)
362 	__raw_writel((val), (atdma)->regs + AT_DMA_##name)
370 /*--  Helper functions  ------------------------------------------------*/
374 	return &chan->dev->device;  in chan2dev()
380 	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);  in vdbg_dump_regs()
382 	dev_err(chan2dev(&atchan->chan_common),  in vdbg_dump_regs()
384 		atchan->chan_common.chan_id,  in vdbg_dump_regs()
388 	dev_err(chan2dev(&atchan->chan_common),  in vdbg_dump_regs()
403 	dev_crit(chan2dev(&atchan->chan_common),  in atc_dump_lli()
405 		 &lli->saddr, &lli->daddr,  in atc_dump_lli()
406 		 lli->ctrla, lli->ctrlb, &lli->dscr);  in atc_dump_lli()
435  * atc_chan_is_enabled - test if given channel is enabled
440 	struct at_dma	*atdma = to_at_dma(atchan->chan_common.device);  in atc_chan_is_enabled()
442 	return !!(dma_readl(atdma, CHSR) & atchan->mask);  in atc_chan_is_enabled()
446  * atc_chan_is_paused - test channel pause/resume status
451 	return test_bit(ATC_IS_PAUSED, &atchan->status);  in atc_chan_is_paused()
455  * atc_chan_is_cyclic - test if given channel has cyclic property set
460 	return test_bit(ATC_IS_CYCLIC, &atchan->status);  in atc_chan_is_cyclic()
464  * set_desc_eol - set end-of-link to descriptor so it will end transfer
469 	u32 ctrlb = desc->lli.ctrlb;  in set_desc_eol()
474 	desc->lli.ctrlb = ctrlb;  in set_desc_eol()
475 	desc->lli.dscr = 0;  in set_desc_eol()