139 static enum dma_transfer_direction admac_chan_direction(int channo)  in admac_chan_direction()  argument
142 	return (channo & 1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;  in admac_chan_direction()
202 static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo,  in admac_cyclic_write_one_desc()  argument
213 		channo, &addr, tx->period_len, FLAG_DESC_NOTIFY);  in admac_cyclic_write_one_desc()
215 	writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));  in admac_cyclic_write_one_desc()
216 	writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));  in admac_cyclic_write_one_desc()
217 	writel_relaxed(tx->period_len,      ad->base + REG_DESC_WRITE(channo));  in admac_cyclic_write_one_desc()
218 	writel_relaxed(FLAG_DESC_NOTIFY,    ad->base + REG_DESC_WRITE(channo));  in admac_cyclic_write_one_desc()
228 static void admac_cyclic_write_desc(struct admac_data *ad, int channo,  in admac_cyclic_write_desc()  argument
234 		if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)  in admac_cyclic_write_desc()
236 		admac_cyclic_write_one_desc(ad, channo, tx);  in admac_cyclic_write_desc()
260 static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo,  in admac_cyclic_read_residue()  argument
268 	ring1 =    readl_relaxed(ad->base + REG_REPORT_RING(channo));  in admac_cyclic_read_residue()
269 	residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));  in admac_cyclic_read_residue()
270 	ring2 =    readl_relaxed(ad->base + REG_REPORT_RING(channo));  in admac_cyclic_read_residue()
271 	residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));  in admac_cyclic_read_residue()
499 static int admac_drain_reports(struct admac_data *ad, int channo)  in admac_drain_reports()  argument
506 		if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)  in admac_drain_reports()
509 		countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));  in admac_drain_reports()
510 		countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));  in admac_drain_reports()
511 		unk1 =        readl_relaxed(ad->base + REG_REPORT_READ(channo));  in admac_drain_reports()
512 		flags =       readl_relaxed(ad->base + REG_REPORT_READ(channo));  in admac_drain_reports()
515 			channo, ((u64) countval_hi) << 32 | countval_lo, unk1, flags);  in admac_drain_reports()
521 static void admac_handle_status_err(struct admac_data *ad, int channo)  in admac_handle_status_err()  argument
525 	if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {  in admac_handle_status_err()
526 		writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));  in admac_handle_status_err()
527 		dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo);  in admac_handle_status_err()
531 	if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {  in admac_handle_status_err()
532 		writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));  in admac_handle_status_err()
533 		dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo);  in admac_handle_status_err()
538 		dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo);  in admac_handle_status_err()
539 		admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index),  in admac_handle_status_err()
544 static void admac_handle_status_desc_done(struct admac_data *ad, int channo)  in admac_handle_status_desc_done()  argument
546 	struct admac_chan *adchan = &ad->channels[channo];  in admac_handle_status_desc_done()
551 		       ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));  in admac_handle_status_desc_done()
554 	nreports = admac_drain_reports(ad, channo);  in admac_handle_status_desc_done()
563 		admac_cyclic_write_desc(ad, channo, tx);  in admac_handle_status_desc_done()