Lines Matching refs:ad
121 static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val) in admac_modify() argument
123 void __iomem *addr = ad->base + reg; in admac_modify()
202 static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo, in admac_cyclic_write_one_desc() argument
212 dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n", in admac_cyclic_write_one_desc()
215 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
216 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
217 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
218 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
228 static void admac_cyclic_write_desc(struct admac_data *ad, int channo, in admac_cyclic_write_desc() argument
234 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL) in admac_cyclic_write_desc()
236 admac_cyclic_write_one_desc(ad, channo, tx); in admac_cyclic_write_desc()
260 static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo, in admac_cyclic_read_residue() argument
268 ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo)); in admac_cyclic_read_residue()
269 residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo)); in admac_cyclic_read_residue()
270 ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo)); in admac_cyclic_read_residue()
271 residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo)); in admac_cyclic_read_residue()
293 struct admac_data *ad = adchan->host; in admac_tx_status() local
309 residue = admac_cyclic_read_residue(ad, adchan->no, adtx); in admac_tx_status()
328 struct admac_data *ad = adchan->host; in admac_start_chan() local
332 ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index)); in admac_start_chan()
334 ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index)); in admac_start_chan()
338 writel_relaxed(startbit, ad->base + REG_TX_START); in admac_start_chan()
341 writel_relaxed(startbit, ad->base + REG_RX_START); in admac_start_chan()
351 struct admac_data *ad = adchan->host; in admac_stop_chan() local
356 writel_relaxed(stopbit, ad->base + REG_TX_STOP); in admac_stop_chan()
359 writel_relaxed(stopbit, ad->base + REG_RX_STOP); in admac_stop_chan()
369 struct admac_data *ad = adchan->host; in admac_reset_rings() local
372 ad->base + REG_CHAN_CTL(adchan->no)); in admac_reset_rings()
373 writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no)); in admac_reset_rings()
378 struct admac_data *ad = adchan->host; in admac_start_current_tx() local
382 writel_relaxed(0, ad->base + REG_CHAN_CTL(ch)); in admac_start_current_tx()
384 admac_cyclic_write_one_desc(ad, ch, adchan->current_tx); in admac_start_current_tx()
386 admac_cyclic_write_desc(ad, ch, adchan->current_tx); in admac_start_current_tx()
483 struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data; in admac_dma_of_xlate() local
491 if (index >= ad->nchannels) { in admac_dma_of_xlate()
492 dev_err(ad->dev, "channel index %u out of bounds\n", index); in admac_dma_of_xlate()
496 return dma_get_slave_channel(&ad->channels[index].chan); in admac_dma_of_xlate()
499 static int admac_drain_reports(struct admac_data *ad, int channo) in admac_drain_reports() argument
506 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY) in admac_drain_reports()
509 countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
510 countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
511 unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
512 flags = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
514 dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n", in admac_drain_reports()
521 static void admac_handle_status_err(struct admac_data *ad, int channo) in admac_handle_status_err() argument
525 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) { in admac_handle_status_err()
526 writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo)); in admac_handle_status_err()
527 dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo); in admac_handle_status_err()
531 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) { in admac_handle_status_err()
532 writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo)); in admac_handle_status_err()
533 dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo); in admac_handle_status_err()
538 dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo); in admac_handle_status_err()
539 admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index), in admac_handle_status_err()
544 static void admac_handle_status_desc_done(struct admac_data *ad, int channo) in admac_handle_status_desc_done() argument
546 struct admac_chan *adchan = &ad->channels[channo]; in admac_handle_status_desc_done()
551 ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index)); in admac_handle_status_desc_done()
554 nreports = admac_drain_reports(ad, channo); in admac_handle_status_desc_done()
563 admac_cyclic_write_desc(ad, channo, tx); in admac_handle_status_desc_done()
569 static void admac_handle_chan_int(struct admac_data *ad, int no) in admac_handle_chan_int() argument
571 u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index)); in admac_handle_chan_int()
574 admac_handle_status_err(ad, no); in admac_handle_chan_int()
577 admac_handle_status_desc_done(ad, no); in admac_handle_chan_int()
582 struct admac_data *ad = devid; in admac_interrupt() local
586 rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index)); in admac_interrupt()
587 tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index)); in admac_interrupt()
592 for (i = 0; i < ad->nchannels; i += 2) { in admac_interrupt()
594 admac_handle_chan_int(ad, i); in admac_interrupt()
598 for (i = 1; i < ad->nchannels; i += 2) { in admac_interrupt()
600 admac_handle_chan_int(ad, i); in admac_interrupt()
636 struct admac_data *ad = adchan->host; in admac_device_config() local
678 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no)); in admac_device_config()
689 ad->base + REG_CHAN_FIFOCTL(adchan->no)); in admac_device_config()
697 struct admac_data *ad; in admac_probe() local
708 ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL); in admac_probe()
709 if (!ad) in admac_probe()
712 platform_set_drvdata(pdev, ad); in admac_probe()
713 ad->dev = &pdev->dev; in admac_probe()
714 ad->nchannels = nchannels; in admac_probe()
723 ad->irq_index = i; in admac_probe()
730 ad->irq = irq; in admac_probe()
732 ad->base = devm_platform_ioremap_resource(pdev, 0); in admac_probe()
733 if (IS_ERR(ad->base)) in admac_probe()
734 return dev_err_probe(&pdev->dev, PTR_ERR(ad->base), in admac_probe()
737 ad->rstc = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in admac_probe()
738 if (IS_ERR(ad->rstc)) in admac_probe()
739 return PTR_ERR(ad->rstc); in admac_probe()
741 dma = &ad->dma; in admac_probe()
766 struct admac_chan *adchan = &ad->channels[i]; in admac_probe()
768 adchan->host = ad; in admac_probe()
770 adchan->chan.device = &ad->dma; in admac_probe()
779 err = reset_control_reset(ad->rstc); in admac_probe()
784 err = request_irq(irq, admac_interrupt, 0, dev_name(&pdev->dev), ad); in admac_probe()
791 err = dma_async_device_register(&ad->dma); in admac_probe()
797 err = of_dma_controller_register(pdev->dev.of_node, admac_dma_of_xlate, ad); in admac_probe()
799 dma_async_device_unregister(&ad->dma); in admac_probe()
807 free_irq(ad->irq, ad); in admac_probe()
809 reset_control_rearm(ad->rstc); in admac_probe()
815 struct admac_data *ad = platform_get_drvdata(pdev); in admac_remove() local
818 dma_async_device_unregister(&ad->dma); in admac_remove()
819 free_irq(ad->irq, ad); in admac_remove()
820 reset_control_rearm(ad->rstc); in admac_remove()