Lines Matching full:decoder

39 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
71 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
155 	 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
229  * decoder supports as well as configuration lock status See "CXL 2.0
230  * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
254  * struct cxl_decoder - Common CXL HDM Decoder Attributes
255  * @dev: this decoder's device
257  * @hpa_range: Host physical address range mapped by this decoder
261  * @region: currently assigned region for this decoder
263  * @commit: device/decoder-type specific callback to commit settings to hw
264  * @reset: device/decoder-type specific callback to reset hw settings
292  * struct cxl_endpoint_decoder - Endpoint  / SPA to DPA decoder
294  * @dpa_res: actively claimed DPA span of this decoder
296  * @mode: which memory type / access-mode-partition this decoder targets
308  * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
312  * @target: active ordered target list in current decoder configuration
314  * The 'switch' decoder type represents the decoder instances of cxl_port's that
329  * struct cxl_root_decoder - Static platform CXL address decoder
333  * @cxlsd: base cxl switch decoder
367  * @targets: active ordered targets in current decoder configuration
386  * @mode: Endpoint decoder allocation / access mode
387  * @type: Endpoint decoder target type
459  * @decoder_ida: allocator for decoder ids
461  * @hdm_end: track last allocated HDM decoder instance for allocation ordering
462  * @commit_end: cursor to track highest committed decoder for commit ordering
501  * @port_id: unique hardware identifier for dport in decoder target list
528  * @decoder: decoder assigned for @region in @port
537 	struct cxl_decoder *decoder;  member