1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/io-64-nonatomic-lo-hi.h>
7 #include <linux/pci-doe.h>
16  * Compute Express Link protocols are layered on top of PCIe. CXL core provides
35 	struct cxl_port *port = ctx->port;  in match_add_dports()
42 	if (pdev->bus != ctx->bus)  in match_add_dports()
46 	if (type != ctx->type)  in match_add_dports()
54 		dev_dbg(&port->dev, "failed to find component registers\n");  in match_add_dports()
57 	dport = devm_cxl_add_dport(port, &pdev->dev, port_num,  in match_add_dports()
60 		ctx->error = PTR_ERR(dport);  in match_add_dports()
63 	ctx->count++;  in match_add_dports()
65 	dev_dbg(&port->dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));  in match_add_dports()
71  * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port
72  * @port: cxl_port whose ->uport is the upstream of dports to be enumerated
84 		return -ENXIO;  in devm_cxl_port_enumerate_dports()
99 		return -ENODEV;  in devm_cxl_port_enumerate_dports()
112 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);  in cxl_await_media_ready()
113 	int d = cxlds->cxl_dvsec;  in cxl_await_media_ready()
118 	for (i = media_ready_timeout; i; i--) {  in cxl_await_media_ready()
133 		dev_err(&pdev->dev,  in cxl_await_media_ready()
136 		return -ETIMEDOUT;  in cxl_await_media_ready()
139 	md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);  in cxl_await_media_ready()
141 		return -EIO;  in cxl_await_media_ready()
149 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);  in wait_for_valid()
150 	int d = cxlds->cxl_dvsec, rc;  in wait_for_valid()
176 	return -ETIMEDOUT;  in wait_for_valid()
181 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);  in cxl_set_mem_enable()
182 	int d = cxlds->cxl_dvsec;  in cxl_set_mem_enable()
221 	return r1->start <= r2->start && r1->end >= r2->end;  in range_contains()
235 	if (!(cxld->flags & CXL_DECODER_F_LOCK))  in dvsec_range_allowed()
237 	if (!(cxld->flags & CXL_DECODER_F_RAM))  in dvsec_range_allowed()
240 	return range_contains(&cxld->hpa_range, dev_range);  in dvsec_range_allowed()
247 	void __iomem *hdm = cxlhdm->regs.hdm_decoder;  in disable_hdm()
256 	void __iomem *hdm = cxlhdm->regs.hdm_decoder;  in devm_cxl_enable_hdm()
270 	void __iomem *hdm = cxlhdm->regs.hdm_decoder;  in __cxl_hdm_decode_init()
271 	struct cxl_port *port = cxlhdm->port;  in __cxl_hdm_decode_init()
272 	struct device *dev = cxlds->dev;  in __cxl_hdm_decode_init()
284 		rc = devm_cxl_enable_mem(&port->dev, cxlds);  in __cxl_hdm_decode_init()
290 	root = to_cxl_port(port->dev.parent);  in __cxl_hdm_decode_init()
291 	while (!is_cxl_root(root) && is_cxl_port(root->dev.parent))  in __cxl_hdm_decode_init()
292 		root = to_cxl_port(root->dev.parent);  in __cxl_hdm_decode_init()
298 	for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) {  in __cxl_hdm_decode_init()
301 		cxld_dev = device_find_child(&root->dev, &info->dvsec_range[i],  in __cxl_hdm_decode_init()
314 		info->mem_enabled = 0;  in __cxl_hdm_decode_init()
321 	 * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges  in __cxl_hdm_decode_init()
326 	if (info->mem_enabled)  in __cxl_hdm_decode_init()
329 	rc = devm_cxl_enable_hdm(&port->dev, cxlhdm);  in __cxl_hdm_decode_init()
333 	rc = devm_cxl_enable_mem(&port->dev, cxlds);  in __cxl_hdm_decode_init()
341  * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
349 	struct pci_dev *pdev = to_pci_dev(cxlds->dev);  in cxl_hdm_decode_init()
352 	struct device *dev = &pdev->dev;  in cxl_hdm_decode_init()
353 	int d = cxlds->cxl_dvsec;  in cxl_hdm_decode_init()
358 		return -ENXIO;  in cxl_hdm_decode_init()
371 		return -ENXIO;  in cxl_hdm_decode_init()
376 	 * HDM decoders (values > 2 are also undefined as of CXL 2.0). As this  in cxl_hdm_decode_init()
381 	if (!hdm_count || hdm_count > 2)  in cxl_hdm_decode_init()
382 		return -EINVAL;  in cxl_hdm_decode_init()
433 			.end = base + size - 1  in cxl_hdm_decode_init()
450 		return -EBUSY;  in cxl_hdm_decode_init()
463 #define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
473 	cxlds = cxlmd->cxlds;  in find_cdat_doe()
475 	xa_for_each(&cxlds->doe_mbs, index, entry) {  in find_cdat_doe()
495 	complete(task->private);  in cxl_doe_task_complete()
535 		return -EIO;  in cxl_cdat_get_length()
547 	size_t length = cdat->length;  in cxl_cdat_read_table()
548 	u32 *data = cdat->table;  in cxl_cdat_read_table()
564 		if (t.task.rv < (2 * sizeof(u32)))  in cxl_cdat_read_table()
565 			return -EIO;  in cxl_cdat_read_table()
573 		entry_dw -= 1;  in cxl_cdat_read_table()
578 			length -= entry_dw * sizeof(u32);  in cxl_cdat_read_table()
587  * read_cdat_data - Read the CDAT data on this port
595 	struct device *dev = &port->dev;  in read_cdat_data()
596 	struct device *uport = port->uport;  in read_cdat_data()
606 	port->cdat_available = true;  in read_cdat_data()
613 	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);  in read_cdat_data()
614 	if (!port->cdat.table)  in read_cdat_data()
617 	port->cdat.length = cdat_length;  in read_cdat_data()
618 	rc = cxl_cdat_read_table(dev, cdat_doe, &port->cdat);  in read_cdat_data()
621 		devm_kfree(dev, port->cdat.table);  in read_cdat_data()
622 		port->cdat.table = NULL;  in read_cdat_data()
623 		port->cdat.length = 0;  in read_cdat_data()