Lines Matching full:memory
11 memory targets, the CXL.io protocol is equivalent to PCI Express.
21 The CXL specification defines a "CXL memory device" sub-class in the
22 PCI "memory controller" base class of devices. Device's identified by
24 memory to be mapped into the system address map (Host-managed Device
25 Memory (HDM)).
27 Say 'y/m' to enable a driver that will attach to CXL memory expander
28 devices enumerated by the memory device class code for configuration
35 bool "RAW Command Interface for Memory Devices"
48 potential impact to memory currently in use by the kernel.
58 Enable support for host managed device memory (HDM) resources
59 published by a platform's ACPI CXL memory layout description. See
61 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
65 Memory regions to be managed by LIBNVDIMM.
70 tristate "CXL PMEM: Persistent Memory Support"
74 In addition to typical memory resources a platform may also advertise
75 support for persistent memory attached via CXL. This support is
78 provisioning the persistent memory capacity of CXL memory expanders.
83 tristate "CXL: Memory Expansion"
88 RAM" and/or "Persistent Memory" that is fully coherent as if the
89 memory were attached to the typical CPU memory controller. This is
90 known as HDM "Host-managed Device Memory".
93 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0