Lines Matching full:handle
36 #define AE(handle, ae) ((handle)->hal_handle->aes[ae]) argument
69 void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_live_ctx() argument
72 AE(handle, ae).live_ctx_mask = ctx_mask; in qat_hal_set_live_ctx()
76 static int qat_hal_rd_ae_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_rd_ae_csr() argument
83 value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
84 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) in qat_hal_rd_ae_csr()
92 static int qat_hal_wr_ae_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_ae_csr() argument
99 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
100 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) in qat_hal_wr_ae_csr()
108 static void qat_hal_get_wakeup_event(struct icp_qat_fw_loader_handle *handle, in qat_hal_get_wakeup_event() argument
114 cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); in qat_hal_get_wakeup_event()
115 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_get_wakeup_event()
116 *events = qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT); in qat_hal_get_wakeup_event()
117 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_get_wakeup_event()
120 static int qat_hal_wait_cycles(struct icp_qat_fw_loader_handle *handle, in qat_hal_wait_cycles() argument
129 base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); in qat_hal_wait_cycles()
133 csr = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); in qat_hal_wait_cycles()
135 cur_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); in qat_hal_wait_cycles()
156 int qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_ctx_mode() argument
167 csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_set_ae_ctx_mode()
172 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_ctx_mode()
176 int qat_hal_set_ae_nn_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_nn_mode() argument
181 csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_set_ae_nn_mode()
189 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_nn_mode()
194 int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_lm_mode() argument
200 csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_set_ae_lm_mode()
229 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_lm_mode()
233 void qat_hal_set_ae_tindex_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_tindex_mode() argument
238 csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_set_ae_tindex_mode()
244 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_tindex_mode()
302 void qat_hal_reset(struct icp_qat_fw_loader_handle *handle) in qat_hal_reset() argument
304 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_reset()
305 unsigned int reset_csr = handle->chip_info->icp_rst_csr; in qat_hal_reset()
308 csr_val = GET_CAP_CSR(handle, reset_csr); in qat_hal_reset()
310 SET_CAP_CSR(handle, reset_csr, csr_val); in qat_hal_reset()
313 static void qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_indr_csr() argument
319 cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); in qat_hal_wr_indr_csr()
324 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_wr_indr_csr()
325 qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val); in qat_hal_wr_indr_csr()
328 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_wr_indr_csr()
331 static unsigned int qat_hal_rd_indr_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_rd_indr_csr() argument
337 cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); in qat_hal_rd_indr_csr()
338 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_rd_indr_csr()
339 csr_val = qat_hal_rd_ae_csr(handle, ae, ae_csr); in qat_hal_rd_indr_csr()
340 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_rd_indr_csr()
345 static void qat_hal_put_sig_event(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_sig_event() argument
351 cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); in qat_hal_put_sig_event()
355 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_put_sig_event()
356 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_INDIRECT, events); in qat_hal_put_sig_event()
358 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_put_sig_event()
361 static void qat_hal_put_wakeup_event(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_wakeup_event() argument
367 cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER); in qat_hal_put_wakeup_event()
371 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_put_wakeup_event()
372 qat_hal_wr_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, in qat_hal_put_wakeup_event()
375 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_put_wakeup_event()
378 static int qat_hal_check_ae_alive(struct icp_qat_fw_loader_handle *handle) in qat_hal_check_ae_alive() argument
380 unsigned long ae_mask = handle->hal_handle->ae_mask; in qat_hal_check_ae_alive()
385 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_check_ae_alive()
386 base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); in qat_hal_check_ae_alive()
390 cur_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); in qat_hal_check_ae_alive()
403 int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle, in qat_hal_check_ae_active() argument
408 enable = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_check_ae_active()
409 active = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); in qat_hal_check_ae_active()
417 static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) in qat_hal_reset_timestamp() argument
419 unsigned long ae_mask = handle->hal_handle->ae_mask; in qat_hal_reset_timestamp()
423 misc_ctl_csr = handle->chip_info->misc_ctl_csr; in qat_hal_reset_timestamp()
425 misc_ctl = GET_CAP_CSR(handle, misc_ctl_csr); in qat_hal_reset_timestamp()
427 SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl & in qat_hal_reset_timestamp()
430 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_reset_timestamp()
431 qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); in qat_hal_reset_timestamp()
432 qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0); in qat_hal_reset_timestamp()
435 SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl | MC_TIMESTAMP_ENABLE); in qat_hal_reset_timestamp()
442 static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle) in qat_hal_init_esram() argument
445 (void __iomem *)((uintptr_t)handle->hal_ep_csr_addr_v + in qat_hal_init_esram()
450 if (handle->pci_dev->device != PCI_DEVICE_ID_INTEL_QAT_DH895XCC) in qat_hal_init_esram()
462 qat_hal_wait_cycles(handle, 0, ESRAM_AUTO_INIT_USED_CYCLES, 0); in qat_hal_init_esram()
473 int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) in qat_hal_clr_reset() argument
475 unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr; in qat_hal_clr_reset()
476 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_clr_reset()
477 unsigned int reset_csr = handle->chip_info->icp_rst_csr; in qat_hal_clr_reset()
478 unsigned long ae_mask = handle->hal_handle->ae_mask; in qat_hal_clr_reset()
484 csr_val = GET_CAP_CSR(handle, reset_csr); in qat_hal_clr_reset()
487 SET_CAP_CSR(handle, reset_csr, csr_val); in qat_hal_clr_reset()
490 csr_val = GET_CAP_CSR(handle, reset_csr); in qat_hal_clr_reset()
494 csr_val = GET_CAP_CSR(handle, clk_csr); in qat_hal_clr_reset()
496 SET_CAP_CSR(handle, clk_csr, csr_val); in qat_hal_clr_reset()
497 if (qat_hal_check_ae_alive(handle)) in qat_hal_clr_reset()
501 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_clr_reset()
502 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, in qat_hal_clr_reset()
504 qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX, in qat_hal_clr_reset()
506 handle->hal_handle->upc_mask & in qat_hal_clr_reset()
508 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE); in qat_hal_clr_reset()
509 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE); in qat_hal_clr_reset()
510 qat_hal_put_wakeup_event(handle, ae, in qat_hal_clr_reset()
513 qat_hal_put_sig_event(handle, ae, in qat_hal_clr_reset()
517 if (qat_hal_init_esram(handle)) in qat_hal_clr_reset()
519 if (qat_hal_wait_cycles(handle, 0, SHRAM_INIT_CYCLES, 0)) in qat_hal_clr_reset()
521 qat_hal_reset_timestamp(handle); in qat_hal_clr_reset()
529 static void qat_hal_disable_ctx(struct icp_qat_fw_loader_handle *handle, in qat_hal_disable_ctx() argument
534 ctx = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_disable_ctx()
537 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); in qat_hal_disable_ctx()
570 void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_uwords() argument
577 ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); in qat_hal_wr_uwords()
579 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_wr_uwords()
587 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); in qat_hal_wr_uwords()
588 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); in qat_hal_wr_uwords()
590 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_wr_uwords()
593 static void qat_hal_enable_ctx(struct icp_qat_fw_loader_handle *handle, in qat_hal_enable_ctx() argument
598 ctx = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_enable_ctx()
602 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); in qat_hal_enable_ctx()
605 static void qat_hal_clear_xfer(struct icp_qat_fw_loader_handle *handle) in qat_hal_clear_xfer() argument
607 unsigned long ae_mask = handle->hal_handle->ae_mask; in qat_hal_clear_xfer()
611 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_clear_xfer()
613 qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS, in qat_hal_clear_xfer()
615 qat_hal_init_rd_xfer(handle, ae, 0, ICP_DR_RD_ABS, in qat_hal_clear_xfer()
621 static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) in qat_hal_clear_gpr() argument
623 unsigned long ae_mask = handle->hal_handle->ae_mask; in qat_hal_clear_gpr()
631 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_clear_gpr()
632 csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); in qat_hal_clear_gpr()
634 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); in qat_hal_clear_gpr()
635 csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_clear_gpr()
637 if (handle->chip_info->nn) in qat_hal_clear_gpr()
640 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val); in qat_hal_clear_gpr()
641 qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst), in qat_hal_clear_gpr()
643 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, in qat_hal_clear_gpr()
644 handle->hal_handle->upc_mask & in qat_hal_clear_gpr()
646 savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); in qat_hal_clear_gpr()
647 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0); in qat_hal_clear_gpr()
648 qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY); in qat_hal_clear_gpr()
649 qat_hal_wr_indr_csr(handle, ae, ctx_mask, in qat_hal_clear_gpr()
651 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); in qat_hal_clear_gpr()
652 qat_hal_enable_ctx(handle, ae, ctx_mask); in qat_hal_clear_gpr()
654 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_clear_gpr()
657 ret = qat_hal_wait_cycles(handle, ae, 20, 1); in qat_hal_clear_gpr()
664 qat_hal_disable_ctx(handle, ae, ctx_mask); in qat_hal_clear_gpr()
665 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, in qat_hal_clear_gpr()
667 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, in qat_hal_clear_gpr()
669 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, in qat_hal_clear_gpr()
670 handle->hal_handle->upc_mask & in qat_hal_clear_gpr()
672 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE); in qat_hal_clear_gpr()
673 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE); in qat_hal_clear_gpr()
674 qat_hal_put_wakeup_event(handle, ae, ctx_mask, in qat_hal_clear_gpr()
676 qat_hal_put_sig_event(handle, ae, ctx_mask, in qat_hal_clear_gpr()
682 static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, in qat_hal_chip_init() argument
695 handle->pci_dev = pci_info->pci_dev; in qat_hal_chip_init()
696 switch (handle->pci_dev->device) { in qat_hal_chip_init()
699 handle->chip_info->mmp_sram_size = 0; in qat_hal_chip_init()
700 handle->chip_info->nn = false; in qat_hal_chip_init()
701 handle->chip_info->lm2lm3 = true; in qat_hal_chip_init()
702 handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X; in qat_hal_chip_init()
703 handle->chip_info->icp_rst_csr = ICP_RESET_CPP0; in qat_hal_chip_init()
704 handle->chip_info->icp_rst_mask = 0x100015; in qat_hal_chip_init()
705 handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE_CPP0; in qat_hal_chip_init()
706 handle->chip_info->misc_ctl_csr = MISC_CONTROL_C4XXX; in qat_hal_chip_init()
707 handle->chip_info->wakeup_event_val = 0x80000000; in qat_hal_chip_init()
708 handle->chip_info->fw_auth = true; in qat_hal_chip_init()
709 handle->chip_info->css_3k = true; in qat_hal_chip_init()
710 handle->chip_info->tgroup_share_ustore = true; in qat_hal_chip_init()
711 handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX; in qat_hal_chip_init()
712 handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX; in qat_hal_chip_init()
713 handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI_4XXX; in qat_hal_chip_init()
714 handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO_4XXX; in qat_hal_chip_init()
715 handle->chip_info->fcu_loaded_ae_csr = FCU_AE_LOADED_4XXX; in qat_hal_chip_init()
716 handle->chip_info->fcu_loaded_ae_pos = 0; in qat_hal_chip_init()
718 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET_4XXX; in qat_hal_chip_init()
719 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET_4XXX; in qat_hal_chip_init()
720 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET_4XXX; in qat_hal_chip_init()
721 handle->hal_cap_ae_local_csr_addr_v = in qat_hal_chip_init()
722 (void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v in qat_hal_chip_init()
727 handle->chip_info->mmp_sram_size = 0; in qat_hal_chip_init()
728 handle->chip_info->nn = true; in qat_hal_chip_init()
729 handle->chip_info->lm2lm3 = false; in qat_hal_chip_init()
730 handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; in qat_hal_chip_init()
731 handle->chip_info->icp_rst_csr = ICP_RESET; in qat_hal_chip_init()
732 handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) | in qat_hal_chip_init()
734 handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE; in qat_hal_chip_init()
735 handle->chip_info->misc_ctl_csr = MISC_CONTROL; in qat_hal_chip_init()
736 handle->chip_info->wakeup_event_val = WAKEUP_EVENT; in qat_hal_chip_init()
737 handle->chip_info->fw_auth = true; in qat_hal_chip_init()
738 handle->chip_info->css_3k = false; in qat_hal_chip_init()
739 handle->chip_info->tgroup_share_ustore = false; in qat_hal_chip_init()
740 handle->chip_info->fcu_ctl_csr = FCU_CONTROL; in qat_hal_chip_init()
741 handle->chip_info->fcu_sts_csr = FCU_STATUS; in qat_hal_chip_init()
742 handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI; in qat_hal_chip_init()
743 handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO; in qat_hal_chip_init()
744 handle->chip_info->fcu_loaded_ae_csr = FCU_STATUS; in qat_hal_chip_init()
745 handle->chip_info->fcu_loaded_ae_pos = FCU_LOADED_AE_POS; in qat_hal_chip_init()
746 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET; in qat_hal_chip_init()
747 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET; in qat_hal_chip_init()
748 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET; in qat_hal_chip_init()
749 handle->hal_cap_ae_local_csr_addr_v = in qat_hal_chip_init()
750 (void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v in qat_hal_chip_init()
754 handle->chip_info->mmp_sram_size = 0x40000; in qat_hal_chip_init()
755 handle->chip_info->nn = true; in qat_hal_chip_init()
756 handle->chip_info->lm2lm3 = false; in qat_hal_chip_init()
757 handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; in qat_hal_chip_init()
758 handle->chip_info->icp_rst_csr = ICP_RESET; in qat_hal_chip_init()
759 handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) | in qat_hal_chip_init()
761 handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE; in qat_hal_chip_init()
762 handle->chip_info->misc_ctl_csr = MISC_CONTROL; in qat_hal_chip_init()
763 handle->chip_info->wakeup_event_val = WAKEUP_EVENT; in qat_hal_chip_init()
764 handle->chip_info->fw_auth = false; in qat_hal_chip_init()
765 handle->chip_info->css_3k = false; in qat_hal_chip_init()
766 handle->chip_info->tgroup_share_ustore = false; in qat_hal_chip_init()
767 handle->chip_info->fcu_ctl_csr = 0; in qat_hal_chip_init()
768 handle->chip_info->fcu_sts_csr = 0; in qat_hal_chip_init()
769 handle->chip_info->fcu_dram_addr_hi = 0; in qat_hal_chip_init()
770 handle->chip_info->fcu_dram_addr_lo = 0; in qat_hal_chip_init()
771 handle->chip_info->fcu_loaded_ae_csr = 0; in qat_hal_chip_init()
772 handle->chip_info->fcu_loaded_ae_pos = 0; in qat_hal_chip_init()
773 handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET; in qat_hal_chip_init()
774 handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET; in qat_hal_chip_init()
775 handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET; in qat_hal_chip_init()
776 handle->hal_cap_ae_local_csr_addr_v = in qat_hal_chip_init()
777 (void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v in qat_hal_chip_init()
785 if (handle->chip_info->mmp_sram_size > 0) { in qat_hal_chip_init()
788 handle->hal_sram_addr_v = sram_bar->virt_addr; in qat_hal_chip_init()
790 handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid; in qat_hal_chip_init()
791 handle->hal_handle->ae_mask = hw_data->ae_mask; in qat_hal_chip_init()
792 handle->hal_handle->admin_ae_mask = hw_data->admin_ae_mask; in qat_hal_chip_init()
793 handle->hal_handle->slice_mask = hw_data->accel_mask; in qat_hal_chip_init()
794 handle->cfg_ae_mask = ALL_AE_MASK; in qat_hal_chip_init()
796 handle->hal_handle->upc_mask = 0x1ffff; in qat_hal_chip_init()
797 handle->hal_handle->max_ustore = 0x4000; in qat_hal_chip_init()
799 ae_mask = handle->hal_handle->ae_mask; in qat_hal_chip_init()
801 handle->hal_handle->aes[ae].free_addr = 0; in qat_hal_chip_init()
802 handle->hal_handle->aes[ae].free_size = in qat_hal_chip_init()
803 handle->hal_handle->max_ustore; in qat_hal_chip_init()
804 handle->hal_handle->aes[ae].ustore_size = in qat_hal_chip_init()
805 handle->hal_handle->max_ustore; in qat_hal_chip_init()
806 handle->hal_handle->aes[ae].live_ctx_mask = in qat_hal_chip_init()
810 handle->hal_handle->ae_max_num = max_en_ae_id + 1; in qat_hal_chip_init()
813 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_chip_init()
814 csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE); in qat_hal_chip_init()
816 qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); in qat_hal_chip_init()
824 struct icp_qat_fw_loader_handle *handle; in qat_hal_init() local
827 handle = kzalloc(sizeof(*handle), GFP_KERNEL); in qat_hal_init()
828 if (!handle) in qat_hal_init()
831 handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL); in qat_hal_init()
832 if (!handle->hal_handle) { in qat_hal_init()
837 handle->chip_info = kzalloc(sizeof(*handle->chip_info), GFP_KERNEL); in qat_hal_init()
838 if (!handle->chip_info) { in qat_hal_init()
843 ret = qat_hal_chip_init(handle, accel_dev); in qat_hal_init()
850 ret = qat_hal_clr_reset(handle); in qat_hal_init()
856 qat_hal_clear_xfer(handle); in qat_hal_init()
857 if (!handle->chip_info->fw_auth) { in qat_hal_init()
858 ret = qat_hal_clear_gpr(handle); in qat_hal_init()
863 accel_dev->fw_loader->fw_loader = handle; in qat_hal_init()
867 kfree(handle->chip_info); in qat_hal_init()
869 kfree(handle->hal_handle); in qat_hal_init()
871 kfree(handle); in qat_hal_init()
875 void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle) in qat_hal_deinit() argument
877 if (!handle) in qat_hal_deinit()
879 kfree(handle->chip_info); in qat_hal_deinit()
880 kfree(handle->hal_handle); in qat_hal_deinit()
881 kfree(handle); in qat_hal_deinit()
884 int qat_hal_start(struct icp_qat_fw_loader_handle *handle) in qat_hal_start() argument
886 unsigned long ae_mask = handle->hal_handle->ae_mask; in qat_hal_start()
887 u32 wakeup_val = handle->chip_info->wakeup_event_val; in qat_hal_start()
894 if (handle->chip_info->fw_auth) { in qat_hal_start()
895 fcu_ctl_csr = handle->chip_info->fcu_ctl_csr; in qat_hal_start()
896 fcu_sts_csr = handle->chip_info->fcu_sts_csr; in qat_hal_start()
898 SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_START); in qat_hal_start()
901 fcu_sts = GET_CAP_CSR(handle, fcu_sts_csr); in qat_hal_start()
908 for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) { in qat_hal_start()
909 qat_hal_put_wakeup_event(handle, ae, 0, wakeup_val); in qat_hal_start()
910 qat_hal_enable_ctx(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX); in qat_hal_start()
917 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae, in qat_hal_stop() argument
920 if (!handle->chip_info->fw_auth) in qat_hal_stop()
921 qat_hal_disable_ctx(handle, ae, ctx_mask); in qat_hal_stop()
924 void qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_pc() argument
927 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, in qat_hal_set_pc()
928 handle->hal_handle->upc_mask & upc); in qat_hal_set_pc()
931 static void qat_hal_get_uwords(struct icp_qat_fw_loader_handle *handle, in qat_hal_get_uwords() argument
938 misc_control = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); in qat_hal_get_uwords()
939 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, in qat_hal_get_uwords()
941 ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); in qat_hal_get_uwords()
944 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_get_uwords()
946 uwrd_lo = qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER); in qat_hal_get_uwords()
947 uwrd_hi = qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER); in qat_hal_get_uwords()
951 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, misc_control); in qat_hal_get_uwords()
952 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_get_uwords()
955 void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_umem() argument
961 ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); in qat_hal_wr_umem()
963 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_wr_umem()
974 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); in qat_hal_wr_umem()
975 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); in qat_hal_wr_umem()
977 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_wr_umem()
981 static int qat_hal_exec_micro_inst(struct icp_qat_fw_loader_handle *handle, in qat_hal_exec_micro_inst() argument
1000 if ((inst_num > handle->hal_handle->max_ustore) || !micro_inst) { in qat_hal_exec_micro_inst()
1005 ind_lm_addr0 = qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT); in qat_hal_exec_micro_inst()
1006 ind_lm_addr1 = qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT); in qat_hal_exec_micro_inst()
1007 ind_lm_addr_byte0 = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1009 ind_lm_addr_byte1 = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1011 if (handle->chip_info->lm2lm3) { in qat_hal_exec_micro_inst()
1012 ind_lm_addr2 = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1014 ind_lm_addr3 = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1016 ind_lm_addr_byte2 = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1018 ind_lm_addr_byte3 = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1020 ind_t_index = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1022 ind_t_index_byte = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1026 qat_hal_get_uwords(handle, ae, 0, inst_num, savuwords); in qat_hal_exec_micro_inst()
1027 qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events); in qat_hal_exec_micro_inst()
1028 savpc = qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT); in qat_hal_exec_micro_inst()
1029 savpc = (savpc & handle->hal_handle->upc_mask) >> 0; in qat_hal_exec_micro_inst()
1030 ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_exec_micro_inst()
1032 savcc = qat_hal_rd_ae_csr(handle, ae, CC_ENABLE); in qat_hal_exec_micro_inst()
1033 savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); in qat_hal_exec_micro_inst()
1034 ctxarb_ctl = qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL); in qat_hal_exec_micro_inst()
1035 ind_cnt_sig = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1037 ind_sig = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1039 act_sig = qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE); in qat_hal_exec_micro_inst()
1041 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_exec_micro_inst()
1042 qat_hal_wr_uwords(handle, ae, 0, inst_num, micro_inst); in qat_hal_exec_micro_inst()
1043 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 0); in qat_hal_exec_micro_inst()
1044 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO); in qat_hal_exec_micro_inst()
1046 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc & 0xffffdfff); in qat_hal_exec_micro_inst()
1047 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), XCWE_VOLUNTARY); in qat_hal_exec_micro_inst()
1048 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, 0); in qat_hal_exec_micro_inst()
1049 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); in qat_hal_exec_micro_inst()
1050 qat_hal_enable_ctx(handle, ae, (1 << ctx)); in qat_hal_exec_micro_inst()
1052 if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0) in qat_hal_exec_micro_inst()
1057 ctx_status = qat_hal_rd_indr_csr(handle, ae, ctx, in qat_hal_exec_micro_inst()
1059 *endpc = ctx_status & handle->hal_handle->upc_mask; in qat_hal_exec_micro_inst()
1062 qat_hal_disable_ctx(handle, ae, (1 << ctx)); in qat_hal_exec_micro_inst()
1064 qat_hal_wr_uwords(handle, ae, 0, inst_num, savuwords); in qat_hal_exec_micro_inst()
1065 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events); in qat_hal_exec_micro_inst()
1066 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, in qat_hal_exec_micro_inst()
1067 handle->hal_handle->upc_mask & savpc); in qat_hal_exec_micro_inst()
1068 csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); in qat_hal_exec_micro_inst()
1070 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val); in qat_hal_exec_micro_inst()
1071 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc); in qat_hal_exec_micro_inst()
1072 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, savctx & ACS_ACNO); in qat_hal_exec_micro_inst()
1073 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_ctl); in qat_hal_exec_micro_inst()
1074 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
1076 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
1078 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
1080 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
1082 if (handle->chip_info->lm2lm3) { in qat_hal_exec_micro_inst()
1083 qat_hal_wr_indr_csr(handle, ae, BIT(ctx), LM_ADDR_2_INDIRECT, in qat_hal_exec_micro_inst()
1085 qat_hal_wr_indr_csr(handle, ae, BIT(ctx), LM_ADDR_3_INDIRECT, in qat_hal_exec_micro_inst()
1087 qat_hal_wr_indr_csr(handle, ae, BIT(ctx), in qat_hal_exec_micro_inst()
1090 qat_hal_wr_indr_csr(handle, ae, BIT(ctx), in qat_hal_exec_micro_inst()
1093 qat_hal_wr_indr_csr(handle, ae, BIT(ctx), in qat_hal_exec_micro_inst()
1095 qat_hal_wr_indr_csr(handle, ae, BIT(ctx), in qat_hal_exec_micro_inst()
1099 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
1101 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
1103 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig); in qat_hal_exec_micro_inst()
1104 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_exec_micro_inst()
1109 static int qat_hal_rd_rel_reg(struct icp_qat_fw_loader_handle *handle, in qat_hal_rd_rel_reg() argument
1133 savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); in qat_hal_rd_rel_reg()
1134 ctxarb_cntl = qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL); in qat_hal_rd_rel_reg()
1135 ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_rd_rel_reg()
1138 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, in qat_hal_rd_rel_reg()
1140 qat_hal_get_uwords(handle, ae, 0, 1, &savuword); in qat_hal_rd_rel_reg()
1141 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_rd_rel_reg()
1142 ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS); in qat_hal_rd_rel_reg()
1144 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_rd_rel_reg()
1148 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); in qat_hal_rd_rel_reg()
1149 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); in qat_hal_rd_rel_reg()
1150 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_rd_rel_reg()
1152 qat_hal_wait_cycles(handle, ae, 0x8, 0); in qat_hal_rd_rel_reg()
1158 *data = qat_hal_rd_ae_csr(handle, ae, ALU_OUT); in qat_hal_rd_rel_reg()
1159 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_rd_rel_reg()
1160 qat_hal_wr_uwords(handle, ae, 0, 1, &savuword); in qat_hal_rd_rel_reg()
1162 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, in qat_hal_rd_rel_reg()
1164 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_cntl); in qat_hal_rd_rel_reg()
1165 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_rd_rel_reg()
1170 static int qat_hal_wr_rel_reg(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_rel_reg() argument
1213 return qat_hal_exec_micro_inst(handle, ae, ctx, insts, num_inst, in qat_hal_wr_rel_reg()
1251 static int qat_hal_exec_micro_init_lm(struct icp_qat_fw_loader_handle *handle, in qat_hal_exec_micro_init_lm() argument
1261 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, &gpra0); in qat_hal_exec_micro_init_lm()
1262 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, &gpra1); in qat_hal_exec_micro_init_lm()
1263 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, &gpra2); in qat_hal_exec_micro_init_lm()
1264 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, &gprb0); in qat_hal_exec_micro_init_lm()
1265 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, &gprb1); in qat_hal_exec_micro_init_lm()
1268 stat = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, inst_num, 1, in qat_hal_exec_micro_init_lm()
1272 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, gpra0); in qat_hal_exec_micro_init_lm()
1273 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, gpra1); in qat_hal_exec_micro_init_lm()
1274 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, gpra2); in qat_hal_exec_micro_init_lm()
1275 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, gprb0); in qat_hal_exec_micro_init_lm()
1276 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, gprb1); in qat_hal_exec_micro_init_lm()
1281 int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle, in qat_hal_batch_wr_lm() argument
1294 if ((unsigned int)alloc_inst_size > handle->hal_handle->max_ustore) in qat_hal_batch_wr_lm()
1295 alloc_inst_size = handle->hal_handle->max_ustore; in qat_hal_batch_wr_lm()
1316 stat = qat_hal_exec_micro_init_lm(handle, ae, 0, &first_exec, in qat_hal_batch_wr_lm()
1324 static int qat_hal_put_rel_rd_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_rel_rd_xfer() argument
1335 ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_put_rel_rd_xfer()
1352 SET_AE_XFER(handle, ae, reg_addr, val); in qat_hal_put_rel_rd_xfer()
1356 SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val); in qat_hal_put_rel_rd_xfer()
1365 static int qat_hal_put_rel_wr_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_rel_wr_xfer() argument
1385 ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_put_rel_wr_xfer()
1402 status = qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, &gprval); in qat_hal_put_rel_wr_xfer()
1420 status = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, num_inst, in qat_hal_put_rel_wr_xfer()
1422 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, gprval); in qat_hal_put_rel_wr_xfer()
1426 static int qat_hal_put_rel_nn(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_rel_nn() argument
1433 ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_put_rel_nn()
1435 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE); in qat_hal_put_rel_nn()
1437 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val); in qat_hal_put_rel_nn()
1438 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_put_rel_nn()
1443 *handle, unsigned char ae, in qat_hal_convert_abs_to_rel()
1450 ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_convert_abs_to_rel()
1463 int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_gpr() argument
1478 qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, in qat_hal_init_gpr()
1487 stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata); in qat_hal_init_gpr()
1497 int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_wr_xfer() argument
1512 qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, in qat_hal_init_wr_xfer()
1521 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg, in qat_hal_init_wr_xfer()
1532 int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_rd_xfer() argument
1547 qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, in qat_hal_init_rd_xfer()
1556 stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg, in qat_hal_init_rd_xfer()
1567 int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_nn() argument
1573 if (!handle->chip_info->nn) { in qat_hal_init_nn()
1574 dev_err(&handle->pci_dev->dev, "QAT: No next neigh in 0x%x\n", in qat_hal_init_nn()
1575 handle->pci_dev->device); in qat_hal_init_nn()
1585 stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata); in qat_hal_init_nn()