Lines Matching +full:0 +full:x3150
18 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250
22 #define HZIP_CLOCK_GATE_CTRL 0x301004
24 #define HZIP_FSM_MAX_CNT 0x301008
26 #define HZIP_PORT_ARCA_CHE_0 0x301040
27 #define HZIP_PORT_ARCA_CHE_1 0x301044
28 #define HZIP_PORT_AWCA_CHE_0 0x301060
29 #define HZIP_PORT_AWCA_CHE_1 0x301064
30 #define HZIP_CACHE_ALL_EN 0xffffffff
32 #define HZIP_BD_RUSER_32_63 0x301110
33 #define HZIP_SGL_RUSER_32_63 0x30111c
34 #define HZIP_DATA_RUSER_32_63 0x301128
35 #define HZIP_DATA_WUSER_32_63 0x301134
36 #define HZIP_BD_WUSER_32_63 0x301140
38 #define HZIP_QM_IDEL_STATUS 0x3040e4
40 #define HZIP_CORE_DFX_BASE 0x301000
41 #define HZIP_CLOCK_GATED_CONTL 0X301004
42 #define HZIP_CORE_DFX_COMP_0 0x302000
43 #define HZIP_CORE_DFX_COMP_1 0x303000
44 #define HZIP_CORE_DFX_DECOMP_0 0x304000
45 #define HZIP_CORE_DFX_DECOMP_1 0x305000
46 #define HZIP_CORE_DFX_DECOMP_2 0x306000
47 #define HZIP_CORE_DFX_DECOMP_3 0x307000
48 #define HZIP_CORE_DFX_DECOMP_4 0x308000
49 #define HZIP_CORE_DFX_DECOMP_5 0x309000
50 #define HZIP_CORE_REGS_BASE_LEN 0xB0
51 #define HZIP_CORE_REGS_DFX_LEN 0x28
53 #define HZIP_CORE_INT_SOURCE 0x3010A0
54 #define HZIP_CORE_INT_MASK_REG 0x3010A4
55 #define HZIP_CORE_INT_SET 0x3010A8
56 #define HZIP_CORE_INT_STATUS 0x3010AC
58 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148
59 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160
60 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164
61 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168
62 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0
63 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C
66 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0)
69 #define HZIP_PF_DEF_Q_BASE 0
71 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000
72 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0)
73 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C
78 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0)
87 #define HZIP_CNT_CLR_CE_EN BIT(0)
92 #define HZIP_PREFETCH_CFG 0x3011B0
93 #define HZIP_SVA_TRANS 0x3011C4
94 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0)))
103 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8
104 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0)
156 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" },
199 ZIP_QM_NFE_MASK_CAP = 0x0,
225 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77},
226 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77},
227 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
228 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
229 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE},
230 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE},
231 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE},
232 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
233 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1},
234 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2},
235 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5},
236 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2},
237 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3},
238 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C},
239 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3},
240 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF},
241 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF},
242 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},
243 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},
244 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
245 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
246 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
247 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}
262 [HZIP_COMP_CORE0] = 0x302000,
263 [HZIP_COMP_CORE1] = 0x303000,
264 [HZIP_DECOMP_CORE0] = 0x304000,
265 [HZIP_DECOMP_CORE1] = 0x305000,
266 [HZIP_DECOMP_CORE2] = 0x306000,
267 [HZIP_DECOMP_CORE3] = 0x307000,
268 [HZIP_DECOMP_CORE4] = 0x308000,
269 [HZIP_DECOMP_CORE5] = 0x309000,
273 {"HZIP_GET_BD_NUM ", 0x00ull},
274 {"HZIP_GET_RIGHT_BD ", 0x04ull},
275 {"HZIP_GET_ERROR_BD ", 0x08ull},
276 {"HZIP_DONE_BD_NUM ", 0x0cull},
277 {"HZIP_WORK_CYCLE ", 0x10ull},
278 {"HZIP_IDLE_CYCLE ", 0x18ull},
279 {"HZIP_MAX_DELAY ", 0x20ull},
280 {"HZIP_MIN_DELAY ", 0x24ull},
281 {"HZIP_AVG_DELAY ", 0x28ull},
282 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull},
283 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull},
284 {"HZIP_CONSUMED_BYTE ", 0x38ull},
285 {"HZIP_PRODUCED_BYTE ", 0x40ull},
286 {"HZIP_COMP_INF ", 0x70ull},
287 {"HZIP_PRE_OUT ", 0x78ull},
288 {"HZIP_BD_RD ", 0x7cull},
289 {"HZIP_BD_WR ", 0x80ull},
290 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull},
291 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull},
292 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull},
293 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull},
294 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull},
298 {"HZIP_CLOCK_GATE_CTRL ", 0x301004},
299 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160},
300 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164},
301 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168},
302 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C},
306 {"HZIP_GET_BD_NUM ", 0x00ull},
307 {"HZIP_GET_RIGHT_BD ", 0x04ull},
308 {"HZIP_GET_ERROR_BD ", 0x08ull},
309 {"HZIP_DONE_BD_NUM ", 0x0cull},
310 {"HZIP_MAX_DELAY ", 0x20ull},
352 return 0; in hzip_diff_regs_show()
361 * uacce_mode = 0 means zip only register to crypto,
389 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
394 { 0, }
403 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); in zip_create_qps()
425 return 0; in hisi_zip_set_qm_algs()
433 for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) in hisi_zip_set_qm_algs()
439 *ptr = '\0'; in hisi_zip_set_qm_algs()
443 return 0; in hisi_zip_set_qm_algs()
555 return 0; in hisi_zip_set_user_domain_and_cache()
569 val2 = 0x0; in hisi_zip_master_ooo_ctrl()
603 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
635 if (val != 1 && val != 0) in clear_enable_write()
642 return 0; in clear_enable_write()
688 if (*pos != 0) in hisi_zip_ctrl_debug_write()
689 return 0; in hisi_zip_ctrl_debug_write()
695 if (len < 0) in hisi_zip_ctrl_debug_write()
698 tbuf[len] = '\0'; in hisi_zip_ctrl_debug_write()
699 ret = kstrtoul(tbuf, 0, &val); in hisi_zip_ctrl_debug_write()
739 atomic64_set((atomic64_t *)data, 0); in zip_debugfs_atomic64_set()
741 return 0; in zip_debugfs_atomic64_set()
748 return 0; in zip_debugfs_atomic64_get()
758 return 0; in hisi_zip_regs_show()
776 for (i = 0; i < zip_core_num; i++) { in hisi_zip_core_debug_init()
797 return 0; in hisi_zip_core_debug_init()
810 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { in hisi_zip_dfx_debug_init()
869 return 0; in hisi_zip_debugfs_init()
885 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) in hisi_zip_debug_regs_clear()
886 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) in hisi_zip_debug_regs_clear()
891 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
904 qm->debug.curr_qm_qp_num = 0; in hisi_zip_debugfs_exit()
924 for (i = 0; i < com_dfx_regs_num; i++) { in hisi_zip_show_last_regs_init()
929 for (i = 0; i < zip_core_num; i++) { in hisi_zip_show_last_regs_init()
931 for (j = 0; j < core_dfx_regs_num; j++) { in hisi_zip_show_last_regs_init()
938 return 0; in hisi_zip_show_last_regs_init()
966 for (i = 0; i < com_dfx_regs_num; i++) { in hisi_zip_show_last_dfx_regs()
969 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", in hisi_zip_show_last_dfx_regs()
976 for (i = 0; i < zip_core_num; i++) { in hisi_zip_show_last_dfx_regs()
986 for (j = 0; j < core_dfx_regs_num; j++) { in hisi_zip_show_last_dfx_regs()
990 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", in hisi_zip_show_last_dfx_regs()
1005 dev_err(dev, "%s [error status=0x%x] found\n", in hisi_zip_log_hw_error()
1011 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", in hisi_zip_log_hw_error()
1013 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); in hisi_zip_log_hw_error()
1186 /* enable shaper type 0 */ in hisi_zip_probe_init()
1196 return 0; in hisi_zip_probe_init()
1232 if (ret < 0) { in hisi_zip_probe()
1245 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { in hisi_zip_probe()
1247 if (ret < 0) in hisi_zip_probe()
1253 return 0; in hisi_zip_probe()
1340 if (ret < 0) { in hisi_zip_init()