Lines Matching +full:0 +full:x3150
23 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
25 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
26 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
27 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
31 #define SEC_PF_DEF_Q_BASE 0
35 #define SEC_CTRL_CNT_CLR_CE 0x301120
36 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
37 #define SEC_CORE_INT_SOURCE 0x301010
38 #define SEC_CORE_INT_MASK 0x301000
39 #define SEC_CORE_INT_STATUS 0x301008
40 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
42 #define SEC_ECC_MASH 0xFF
43 #define SEC_CORE_INT_DISABLE 0x0
45 #define SEC_RAS_CE_REG 0x301050
46 #define SEC_RAS_FE_REG 0x301054
47 #define SEC_RAS_NFE_REG 0x301058
48 #define SEC_RAS_FE_ENB_MSK 0x0
49 #define SEC_OOO_SHUTDOWN_SEL 0x301014
50 #define SEC_RAS_DISABLE 0x0
51 #define SEC_MEM_START_INIT_REG 0x301100
52 #define SEC_MEM_INIT_DONE_REG 0x301104
55 #define SEC_CONTROL_REG 0x301200
56 #define SEC_DYNAMIC_GATE_REG 0x30121c
57 #define SEC_CORE_AUTO_GATE 0x30212c
58 #define SEC_DYNAMIC_GATE_EN 0x7bff
59 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)
65 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
67 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
68 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
69 #define SEC_SAA_EN_REG 0x301270
70 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
71 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
72 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
79 #define SEC_USER1_WB_DATA_SSV BIT(0)
86 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220
87 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
89 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E
92 #define SEC_PREFETCH_CFG 0x301130
93 #define SEC_SVA_TRANS 0x301EC4
94 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11)))
101 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060
107 #define SEC_DFX_BASE 0x301000
108 #define SEC_DFX_CORE 0x302100
109 #define SEC_DFX_COMMON1 0x301600
110 #define SEC_DFX_COMMON2 0x301C00
111 #define SEC_DFX_BASE_LEN 0x9D
112 #define SEC_DFX_CORE_LEN 0x32B
113 #define SEC_DFX_COMMON1_LEN 0x45
114 #define SEC_DFX_COMMON2_LEN 0xBA
118 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \
150 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77},
151 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77},
152 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
153 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
154 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177},
155 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177},
156 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177},
157 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088},
158 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1},
159 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1},
160 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},
161 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},
162 {SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF},
163 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF},
164 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},
165 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
166 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
167 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
168 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
169 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
170 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
171 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
172 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
173 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
174 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
191 .int_msk = BIT(0),
264 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
265 {"SEC_SAA_EN ", 0x301270},
266 {"SEC_BD_LATENCY_MIN ", 0x301600},
267 {"SEC_BD_LATENCY_MAX ", 0x301608},
268 {"SEC_BD_LATENCY_AVG ", 0x30160C},
269 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
270 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
271 {"SEC_BD_NUM_IN_SEC ", 0x301680},
272 {"SEC_ECC_1BIT_CNT ", 0x301C00},
273 {"SEC_ECC_1BIT_INFO ", 0x301C04},
274 {"SEC_ECC_2BIT_CNT ", 0x301C10},
275 {"SEC_ECC_2BIT_INFO ", 0x301C14},
276 {"SEC_BD_SAA0 ", 0x301C20},
277 {"SEC_BD_SAA1 ", 0x301C24},
278 {"SEC_BD_SAA2 ", 0x301C28},
279 {"SEC_BD_SAA3 ", 0x301C2C},
280 {"SEC_BD_SAA4 ", 0x301C30},
281 {"SEC_BD_SAA5 ", 0x301C34},
282 {"SEC_BD_SAA6 ", 0x301C38},
283 {"SEC_BD_SAA7 ", 0x301C3C},
284 {"SEC_BD_SAA8 ", 0x301C40},
311 return 0; in sec_diff_regs_show()
341 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) { in sec_ctx_q_num_set()
364 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
383 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps); in sec_create_qps()
407 * uacce_mode = 0 means sec only register to crypto,
417 { 0, }
426 reg &= ~(BIT(1) | BIT(0)); in sec_set_endian()
432 reg |= BIT(0); in sec_set_endian()
549 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); in sec_engine_init()
552 reg, reg & 0x1, SEC_DELAY_10_US, in sec_engine_init()
560 reg |= (0x1 << SEC_TRNG_EN_SHIFT); in sec_engine_init()
588 return 0; in sec_engine_init()
622 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
623 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) in sec_debug_regs_clear()
627 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
643 val2 = 0x0; in sec_master_ooo_ctrl()
711 return 0; in sec_clear_enable_write()
758 if (*pos != 0) in sec_debug_write()
759 return 0; in sec_debug_write()
766 if (len < 0) in sec_debug_write()
769 tbuf[len] = '\0'; in sec_debug_write()
770 if (kstrtoul(tbuf, 0, &val)) in sec_debug_write()
809 return 0; in sec_debugfs_atomic64_get()
817 atomic64_set((atomic64_t *)data, 0); in sec_debugfs_atomic64_set()
819 return 0; in sec_debugfs_atomic64_set()
829 return 0; in sec_regs_show()
861 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) { in sec_core_debug_init()
868 return 0; in sec_core_debug_init()
915 return 0; in sec_debugfs_init()
941 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) in sec_show_last_regs_init()
945 return 0; in sec_show_last_regs_init()
970 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) { in sec_show_last_dfx_regs()
973 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n", in sec_show_last_dfx_regs()
986 dev_err(dev, "%s [error status=0x%x] found\n", in sec_log_hw_error()
992 dev_err(dev, "multi ecc sram num=0x%x\n", in sec_log_hw_error()
1040 err_info->msi_wr_port = BIT(0); in sec_err_info_init()
1088 return 0; in sec_set_qm_algs()
1096 for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++) in sec_set_qm_algs()
1102 *ptr = '\0'; in sec_set_qm_algs()
1106 return 0; in sec_set_qm_algs()
1167 /* enable shaper type 0 */ in sec_probe_init()
1174 return 0; in sec_probe_init()
1237 if (ret < 0) { in sec_probe()
1256 if (ret < 0) in sec_probe()
1262 return 0; in sec_probe()
1352 if (ret < 0) { in sec_init()
1358 return 0; in sec_init()